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? 2011 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data this document provides an overview of the mpc8360e/58e powerquicc ii pro processor revision 2.x tbga features, including a block diagram showing the major functional components. this device is a cost-effective, highly integrat ed communications processor that addresses the needs of the networking, wireless infrastructure, and telecommunications markets. target applications include next generation dslams, network interface cards for 3g base stations (node bs), routers, media gateways, and high end iads. the device extends current powerquicc ii pro offerings, adding higher cpu performance, additional func tionality, faster interfaces, and robust interworking between protocols while addressing the requirements related to time-to-market, price, power, and p ackage size. this device can be used for the control plane and also has data plane functionality. for functional characteristics of the processor, refer to the mpc8360e powerquicc ii pro integrated communications processor reference manual , rev. 3. to locate any updates for this document, refer to the mpc8360e product summary page on our website listed on the back cover of this document or contact your freescale sales office. 1 overview this section describes a high-level overview including features and general operation of the mpc8360e/58e powerquicc ii pro processor. a major component of this device is the e300 core, which includes 32 kbytes of instruction and data cach e and is fully compatible with the power architecture? 603e instruction set. the new quicc engine module provides termination, interworking, and switching between a document number: mpc8360eec rev. 5, 09/2011 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. electrical characteristics . . . . . . . . . . . . . . . . . . 7 3. power characteristics . . . . . . . . . . . . . . . . . . . 12 4. clock input timing . . . . . . . . . . . . . . . . . . . . . 14 5. reset initialization . . . . . . . . . . . . . . . . . . . . 16 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . 18 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. ucc ethernet controller: three-speed ethernet, mii management . . . . . . . . . . . . . . . . . . . . . . . 25 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17. tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18. hdlc, bisync, transparent, and synchronous uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 19. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 20. package and pin listings . . . . . . . . . . . . . . . . . 63 21. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 22. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 23. system design information . . . . . . . . . . . . . . . 96 24. ordering information . . . . . . . . . . . . . . . . . . . . 99 25. document revision history . . . . . . . . . . . . . 100 mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 2 freescale semiconductor wide range of protocols including atm, ethernet, hdlc, and pos. the quicc engine module?s enhanced interworking eases the transition and reduces investment cost s from atm to ip based systems. the ot her major features include a dual ddr sdram memory controller for the mpc8360e, which allows equipm ent providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit ddr memory controller for control plane processing and the other for data plane processing. the mpc8358e has a single ddr sdram memory controller. the mpc8360e/58e also offers a 32-bit pci controller, a flexible local bus, and a dedicated security engine. this figure shows the mpc8360eblock diagram. figure 1. mpc8360e block diagram memory controllers gpcm/upm/sdram 32/64 ddr interface unit pci bridge local bus bus arbitration duart dual i2c 4 channel dma interrupt controller protection & configuration system reset clock synthesizer system interface unit (siu) local baud rate generators multi-user ram ucc8 parallel i/o accelerators dual 32-bit risc cp serial dma & 2 virtual dmas 2 gmii/ rgmii/tbi/rtbi 8 mii/ rmii 8 tdm ports 2 utopia/pos (124 mphy) serial interface quicc engine module jtag/cop power management timers fpu classic g2 mmus 32kb d-cache 32kb i-cache security engine e300 core pci ddrc1 ucc7 ucc6 ucc5 ucc4 ucc3 ucc2 ucc1 mcc usb spi2 time slot assigner ddrc2 spi1
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 3 this figure shows the mpc8358e block diagram. figure 2. mpc8358e block diagram major features of the mpc 8360e/58e are as follows: ? e300 powerpc processor core (enhanced version of the mpc603e core) ? operates at up to 667 mhz (for the mp c8360e) and 400 mhz (for the mpc8358e) ? high-performance, supe rscalar processor core ? floating-point, integer, load/store, system register, and branch processing units ? 32-kbyte instruction cach e, 32-kbyte data cache ? lockable portion of l1 cache ? dynamic power management ? software-compatible with the frees cale processor families implementing the power architecture? technology ? quicc engine unit ? two 32-bit risc controllers for flexible support of the communications peripherals, each operating up to 500 mhz (for the mpc8360e) and 400 mhz (for the mpc8358e) ? serial dma channel for receive a nd transmit on all serial channels ? quicc engine module peripheral request interface (for sec, pc i, ieee std. 1588?) ? eight universal communication controllers (uccs) on the mpc8360e and six uccs on the mpc8358e supporting the following protocols and inte rfaces (not all of them simultaneously): ? ieee 1588 protocol supported memory controllers gpcm/upm/sdram 32/64 ddr interface unit pci bridge local bus bus arbitration duart dual i2c 4 channel dma interrupt controller protection & configuration system reset clock synthesizer system interface unit (siu) local baud rate generators multi-user ram ucc8 parallel i/o accelerators dual 32-bit risc cp serial dma & 2 virtual dmas 2 gmii/ rgmii/tbi/rtbi 6 mii/ rmii 4 tdm ports 1 utopia/pos (31/124 mphy) serial interface quicc engine module jtag/cop power management timers fpu classic g2 mmus 32kb d-cache 32kb i-cache security engine e300 core pci ddrc ucc5 ucc4 ucc3 ucc2 ucc1 usb spi2 time slot assigner spi1
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 4 freescale semiconductor ? 10/100 mbps ethern et/ieee std. 802.3? cdma/cs interface th rough a media-indepe ndent interface (mii, rmii, rgmii) 1 ? 1000 mbps ethernet/ieee 802.3 cdma/cs interface thr ough a media-independent interface (gmii, rgmii, tbi, rtbi) on ucc1 and ucc2 ? 9.6-kbyte jumbo frames ? atm full-duplex sar, up to 622 mbps (oc-12/s tm-4), aal0, aal1, and aal5 in accordance itu-t i.363.5 ? atm aal2 cps, sssar, and ssted up to 155 mbps (o c-3/stm-1) mbps full duplex (with 4 cps packets per cell) in accordance it u-t i.366.1 and i.363.2 ? atm traffic shaping for cbr, vbr, ubr, and gfr traffic types compatible with atm forum tm4.1 for up to 64-kbyte simultaneous atm channels ? atm aal1 structured and unstructur ed circuit emulation service (ces 2. 0) in accordance w ith itu-t i.163.1 and atm forum af-vtoa-00-0078.000 ? ima (inverse multiplexing over atm) for up to 31 ima links over 8 ima groups in accordance with the atm forum af-phy-0086.000 (version 1. 0) and af-phy-0086.001 (version 1.1) ? atm transmission convergence layer su pport in accordance with itu-t i.432 ? atm oam handling features compatible with itu-t i.610 ? ppp, multi-link (ml-ppp), multi-cl ass (mc-ppp) and ppp mux in accordance with the following rfcs: 1661, 1662, 1990, 2686, and 3153 ? ip support for ipv4 packets including to s, ttl, and header checksum processing ? ethernet over first mile ieee 802.3ah ? shim header ? ethernet-to-ethernet/aal5/aal2 inter-working ? l2 ethernet switching using mac address or ieee std. 802.1p/q? vlan tags ? atm (aal2/aal5) to ethernet (ip) interworking in accordance with rfc2684 including bridging of atm ports to ethernet ports ? extensive support for atm statistics and ethernet rmon/mib statistics ? aal2 protocol rate up to 4 cps at oc-3/stm-1 rate ? packet over sonet (pos) up to 622-mbps full-duplex 124 multiphy ? pos hardware; microcode must be loaded as an iram package ? transparent up to 70-mbps full-duplex ? hdlc up to 70-mbps full-duplex ? hdlc bus up to 10 mbps ? asynchronous hdlc ?uart ? bisync up to 2 mbps ? user-programmable virtual fifo size ? quicc multichannel controller (qmc) for 64 tdm channels ? one multichannel communication controller (mcc) only on the mpc8360e supporting the following: ? 256 hdlc or transparent channels ? 128 ss7 channels ? almost any combination of subgroups can be mu ltiplexed to single or multiple tdm interfaces ? two utopia/pos interfaces on the mpc8360e suppor ting 124 multiphy each (optio nal 2*128 multiphy with extended address) and one utopia/pos interf ace on the mpc8358e supporting 31/124 multiphy ? two serial peripheral interfaces (spi); spi 2 is dedicated to ethernet phy management 1.smii or sgmii media-independent interface is not currently supported.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 5 ? eight tdm interfaces on the mpc8360e and four tdm interfaces on the mpc8358e with 1-bit mode for e3/t3 rates in clear channel ? sixteen independent baud rate generators and 30 input clock pins for supplying clocks to ucc and mcc serial channels (mcc is only available on the mpc8360e) ? four independent 16-bit timers that can be interconnected as four 32-bit timers ? interworking functionality: ? layer 2 10/100-base t ethernet switch ? atm-to-atm switching (aal0, 2, 5) ? ethernet-to-atm switching with l3/l4 support ? ppp interworking ? security engine is optimized to handl e all the algorithms associated with i psec, ssl/tls, srtp, 802.11i?, iscsi, and ike processing. the security engine contains four crypto-channels, a controll er, and a set of crypto execution units (eus). ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048 bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standard execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits, two key ? ecb, cbc, ccm, and counter modes ? arc four execution unit (afeu) ? implements a stream cipher co mpatible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160-, 224-, or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either sha or md5 algorithm ? random number generator (rng) ? four crypto-channels, each supporti ng multi-command descriptor chains ? static and/or dynamic assignment of crypto -execution units via an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? storage/nas xor parity generation accelerator for raid applications ? dual ddr sdram memory controllers on the mpc8360e and a single ddr sdram memory controller on the mpc8358e ? programmable timing supporting both ddr1 and ddr2 sdram ? on the mpc8360e, the ddr buses can be configured as two 32-bit buses or one 64-bit bus; on the mpc8358e, the ddr bus can be configured as a 32- or 64-bit bus ? 32- or 64-bit data interface, up to 333 mhz (for th e mpc8360e) and 266 mhz (for the mpc8358e) data rate ? four banks of memory , each up to 1 gbyte
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 6 freescale semiconductor ? dram chip configurations from 64 mbits to 1 gigabit with 8/16 data ports ? full ecc support (when the mpc8360e is configured as 232-bit ddr memory controllers, both support ecc) ? page mode support (up to 16 simultaneous open pages for ddr1, up to 32 simultaneous open pages for ddr2) ? contiguous or discontiguous memory mapping ? read-modify-write support ? sleep mode support for self refresh sdram ? supports auto refreshing ? supports source clock mode ? on-the-fly power management using cke ? registered dimm support ? 2.5-v sstl2 compatible i/o for ddr1, 1.8-v sstl2 compatible i/o for ddr2 ? external driver impedance calibration ? on-die termination (odt) ? pci interface ? pci specification revision 2.3 compatible ? data bus widths: ? single 32-bit data pci interface that operates at up to 66 mhz ? pci 3.3-v compatible (not 5-v compatible) ? pci host bridge capab ilities on both interfaces ? pci agent mode supported on pci interface ? support for pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses and support for delayed read transactions ? support for posting of processor-to-pci and pci-to-memory writes ? on-chip arbitration, supporting five masters on pci ? support for accesses to all pci address spaces ? parity support ? selectable hardware-enforced coherency ? address translation units for address mapping between host and peripheral ? dual address cycle supported when the device is the target ? internal configuration registers accessible from pci ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 133 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller ? three protocol engines available on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with configurable bus width (8-, 16-, or 32-bit) ? programmable interrupt controller (pic) ? functional and programming compatibility with the mpc8260 interrupt controller ? support for 8 external and 35 internal discrete interrupt sources ? support for one external (optional) and seven internal machine checkstop interrupt sources
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 7 ? programmable highest priority request ? four groups of interrupts with programmable priority ? external and internal interrupts di rected to communication processor ? redirects interrupts to external inta pin when in core disable mode ? unique vector number for each interrupt source ? dual industry-standard i 2 c interfaces ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? system initialization data is optionally loaded from i 2 c-1 eprom by boot sequencer embedded hardware ? dma controller ? four independent virtual channels ? concurrent execution across multiple channels with programmable bandwidth control ? all channels accessible by local core and remote pci masters ? misaligned tran sfer capability ? data chaining and direct mode ? interrupt on completed segment and chain ? dma external handshake signals: dma_dreq [0:3]/dma_dack [0:3]/dma_done [0:3]. there is one set for each dma channel. the pins are multiplexed to the parallel io pins w ith other qe functions. ?duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compatible with the original 16450 uart and the pc16550d ? system timers ? periodic interrupt timer ? real-time clock ? software watchdog timer ? eight general-purpose timers ? ieee std. 1149.1?-compliant, jtag boundary scan ? integrated pci bus and sdram clock generation 2 electrical characteristics this section provides the ac and dc el ectrical specifications and thermal character istics for the mpc8360e/58e. the device is currently targeted to these specificatio ns. some of these specifications are indepe ndent of the i/o cell, but are included f or a more complete reference. these are not purely i/o buffer design specifications.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 8 freescale semiconductor overall dc electrical characteristics 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings this table provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core and pll supply voltage for mpc8358 device part number with processor frequency label of ad=266mhz and ag=400mhz & quicc engine frequency label of e=300mhz & g=400mhz mpc8360 device part number with processor frequency label of ag=400mhz and aj=533mhz & quicc engine frequency label of g=400mhz v dd & av dd ?0.3 to 1.32 v ? core and pll supply voltage for mpc8360 device part number with processor frequency label of al=667mhz and quicc engine frequency label of h=500mhz v dd & av dd ?0.3 to 1.37 v ? ddr and ddr2 dram i/o voltage ddr ddr2 gv dd ?0.3 to 2.75 ?0.3 to 1.89 v? three-speed ethernet i/o, mii management voltage lv dd ?0.3 to 3.63 v ? pci, local bus, duart, system control and power management, i 2 c, spi, and jtag i/o voltage ov dd ?0.3 to 3.63 v ? input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2 , 5 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2 , 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4 , 5 local bus, duart, clkin, system control and power management, i 2 c, spi, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 3 , 5 pci ov in ?0.3 to (ov dd + 0.3) v 6
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 9 overall dc electrical characteristics 2.1.2 power supply voltage specification this table provides the recommended operating conditions for the de vice. note that the values in this table are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. storage temperature range t stg ?55 to 150 c? notes: 1. functional and tested operating conditions are given in ta bl e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresse s beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: m v in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. caution: lv in must not exceed lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 3 . 6. ov in on the pci interface may overshoot/undershoot according to t he pci electrical specification for 3.3-v operation, as shown in figure 4 . table 2. recommended operating conditions characteristic symbol recommended value unit notes core and pll supply voltage for mpc8358 device part number with processor frequency label of ad=266mhz and ag=400mhz & quicc engine frequency label of e=300mhz & g=400mhz mpc8360 device part number with processor frequency label of ag=400mhz and aj=533mhz & quicc engine frequency label of g=400mhz v dd & av dd 1.2 v 60 mv v 1 , 3 core and pll supply voltage for mpc8360 device part number with processor frequency label of al=667mhz and quicc engine frequency label of h=500mhz v dd & av dd 1.3 v 50 mv v 1 , 3 ddr and ddr2 dram i/o supply voltage ddr ddr2 gv dd 2.5 v 125 mv 1.8 v 90 mv v? three-speed ethernet i/o supply voltage lv dd 0 3.3 v 330 mv 2.5 v 125 mv v? three-speed ethernet i/o supply voltage lv dd 1 3.3 v 330 mv 2.5 v 125 mv v? three-speed ethernet i/o supply voltage lv dd 2 3.3 v 330 mv 2.5 v 125 mv v? table 1. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 10 freescale semiconductor overall dc electrical characteristics this figure shows the undershoot and overshoo t voltages at the interfaces of the device. figure 3. overshoot/undershoot voltage for gv dd /ov dd /lv dd pci, local bus, duart, system control and powe r management, i 2 c, spi, and jtag i/o voltage ov dd 3.3 v 330 mv v ? junction temperature t j 0 to 105 ?40 to 105 c 2 notes: 1. gv dd , lv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction. 2. the operating conditions for junction temperature, t j , on the 600/333/400 mhz and 500/333/500 mhz on rev. 2.0 silicon is 0 to 70 c. refer to errata general9 in chip errata for the mpc8360e, rev. 1 . 3. for more information on part numbering, refer to ta b l e 8 0 . table 2. recommended operating conditions (continued) characteristic symbol recommended value unit notes gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t interface 1 1. note that t interface refers to the clock period associ ated with the bu s clock interface. v ih v il note:
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 11 power sequencing this figure shows the undershoot and overshoot voltage of the pci interface of the device for the 3.3-v si gnals, respectively. figure 4. maximum ac waveforms on pci interface for 3.3-v signaling 2.1.3 output driver characteristics this table provides information on the ch aracteristics of the output dr iver strengths. the values are preliminary estimates. 2.2 power sequencing this section details the power sequenci ng considerations for the mpc8360e/58e. table 3. output drive capability driver type output impedance ( ) supply voltage local bus interface utilities signals 42 ov dd = 3.3 v pci signals 25 pci output clocks (including pci_sync_out) 42 ddr signal 20 36 (half-strength mode) 1 gv dd = 2.5 v ddr2 signal 18 36 (half-strength mode) 1 gv dd = 1.8 v 10/100/1000 ethernet signals 42 lv dd = 2.5/3.3 v duart, system control, i 2 c, spi, jtag 42 ov dd = 3.3 v gpio signals 42 ov dd = 3.3 v lv dd = 2.5/3.3 v note: 1. ddr output impedance values for half strength mode are verified by design and not tested. undervoltage waveform overvoltage waveform 11 ns (min) +7.1 v 7.1 v p-to-p (min) 4 ns (max) ?3.5 v 7.1 v p-to-p (min) 62.5 ns +3.6 v 0 v 4 ns (max)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 12 freescale semiconductor power sequencing 2.2.1 power-up sequencing mpc8360e/58e does not require the core supply voltage (v dd and av dd ) and i/o supply voltages (gv dd , lv dd , and ov dd ) to be applied in any particular order. during the power ramp up , before the power supplies are stable and if the i/o voltages a re supplied before the core voltage, there may be a period of time that all input and output pins are actively be driven and cause contention and excessive current from 3a to 5a. in order to av oid actively driving the i/o pins and to eliminate excessive curr ent draw, apply the core voltage (v dd ) before the i/o voltage (gv dd , lv dd , and ov dd ) and assert poreset before the power supplies fully ramp up. in the case where the core voltage is appl ied first, the core voltage supply must rise to 90% of its no minal value before the i/o supplies reach 0.7 v, see this figure. figure 5. power sequencing example i/o voltage supplies (gv dd , lv dd , and ov dd ) do not have any ordering requirements with respect to one another. 2.2.2 power-down sequencing the mpc8360e/58e does not require the core supply voltage a nd i/o supply voltages to be powered down in any particular order. 3 power characteristics the estimated typical power dissipation values are shown in these tables. table 4. mpc8360e tbga core power dissipation 1 core frequency (mhz) csb frequency (mhz) quicc engine frequency (mhz) typical maximum unit notes 266 266 500 5.0 5.6 w 2 , 3 , 5 400 266 400 4.5 5.0 w 2 , 3 , 4 533 266 400 4.8 5.3 w 2 , 3 , 4 667 333 400 5.8 6.3 w 3 , 6 , 7 , 8 500 333 500 5.9 6.4 w 3 , 6 , 7 , 8 i/o voltage (gv dd , lv dd , ov dd ) core voltage (v dd , av dd ) 90% 0.7 v time voltage
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 13 power sequencing 667 333 500 6.1 6.8 w 2 , 3 , 5 , 9 notes: 1. the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . for i/o power values, see ta b l e 6 . 2. typical power is based on a voltage of v dd = 1.2 v or 1.3 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 3. thermal solutions need to design to a value higher than typical power on the end application, t a target, and i/o power. 4. maximum power is based on a voltage of v dd = 1.2 v, wc process, a junction t j = 105 c, and an artificial smoke test. 5. maximum power is based on a voltage of v dd = 1.3 v for applications that use 667 mhz (cpu)/500 (qe) with wc process, a junction t j = 105 c, and an artificial smoke test. 6. typical power is based on a voltage of v dd = 1.3 v, a junction temperature of t j = 70 c, and a dhrystone benchmark application. 7. maximum power is based on a voltage of v dd = 1.3 v for applications that use 667 mhz (cpu) or 500 (qe) with wc process, a junction t j = 70 c, and an artificial smoke test. 8. this frequency combination is only available for rev. 2.0 silicon. 9. this frequency combination is not available for rev. 2.0 silicon. table 5. mpc8358e tbga core power dissipation 1 core frequency (mhz) csb frequency (mhz) quicc engine frequency (mhz) typical maximum unit notes 266 266 300 4.1 4.5 w 2 , 3 , 4 400 266 400 4.5 5.0 w 2 , 3 , 4 notes: 1. the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . for i/o power values, see ta b l e 6 . 2. typical power is based on a voltage of v dd = 1.2 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 3. thermal solutions need to design to a value higher than typical power on the end application, t a target, and i/o power. 4. maximum power is based on a voltage of v dd = 1.2 v, wc process, a junction t j = 105 c, and an artificial smoke test. table 4. mpc8360e tbga core power dissipation 1 (continued) core frequency (mhz) csb frequency (mhz) quicc engine frequency (mhz) typical maximum unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 14 freescale semiconductor power sequencing this table shows the estimated typical i/o power dissipation for the device. 4 clock input timing this section provides the clock input dc and ac electrical characteristics for the mpc8360e/58e. note the rise/fall time on quicc engine block input pins should not exceed 5 ns. this should be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of v dd ; fall time refers to transitions from 90% to 10% of v dd . table 6. estimated typical i/o power dissipation interface parameter gv dd (1.8 v) gv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) unit comments ddr i/o 65% utilization r s = 20 r t = 50 2 pairs of clocks 200 mhz, 1 32 bits 0.3 0.46 ? ? ? w ? 200 mhz, 1 64 bits 0.4 0.58 ? ? ? w ? 200 mhz, 2 32 bits 0.6 0.92 ? ? ? w ? 266 mhz, 1 32 bits 0.35 0.56 ? ? ? w ? 266 mhz, 1 64 bits 0.46 0.7 ? ? ? w ? 266 mhz, 2 32 bits 0.7 1.11 ? ? ? w ? 333 mhz, 1 32 bits 0.4 0.65 ? ? ? w ? 333 mhz, 1 64 bits 0.53 0.82 ? ? ? w ? 333 mhz, 2 32 bits 0.81 1.3 ? ? ? w ? local bus i/o load = 25 pf 3 pairs of clocks 133 mhz, 32 bits ? ? 0.22 ? ? w ? 83 mhz, 32 bits ? ? 0.14 ? ? w ? 66 mhz, 32 bits ? ? 0.12 ? ? w ? 50 mhz, 32 bits ? ? 0.09 ? ? w ? pci i/o load = 30 pf 33 mhz, 32 bits ? ? 0.05 ? ? w ? 66 mhz, 32 bits ? ? 0.07 ? ? w ? 10/100/1000 ethernet i/o load = 20 pf mii or rmii ? ? ? 0.01 ? w multiply by number of interfaces used. gmii or tbi ? ? ? 0.04 ? w rgmii or rtbi ????0.04w other i/o ? ? ? 0.1 ? ? w ?
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 15 dc electrical characteristics 4.1 dc electrical characteristics this table provides the clock input (clkin/pci_s ync_in) dc timing specifications for the device. 4.2 ac electrical characteristics the primary clock source for the device can be one of two input s, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. this table provides the clock input (clkin/pci_clk) ac timing specifications for the device. 4.3 gigabit referen ce clock input timing this table provides the gigabit reference clocks (gtx_clk125) ac timing specifications. table 7. clkin dc electr ical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.7 ov dd + 0.3 v input low voltage ? v il ?0.3 0.4 v clkin input current 0 v v in ov dd i in ? 1 0 a pci_sync_in input current 0 v v in 0.5v or ov dd ? 0.5v v in ov dd i in ? 1 0 a pci_sync_in input current 0.5 v v in ov dd ? 0.5 v i in ? 100 a table 8. clkin ac timing specifications parameter/condition symbol min typical max unit notes clkin/pci_clk frequency f clkin ? ? 66.67 mhz 1 clkin/pci_clk cycle time t clkin 15 ? ? ns ? clkin/pci_clk rise and fall time t kh , t kl 0.6 1.0 2.3 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitter ? ? ? 150 ps 4 , 5 notes: 1. caution: the system, core, usb, security, and 10/100/1000 ethern et must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for clkin/pci_clk are measured at 0.4 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the clkin/pci_clk driver?s closed loop jitter bandwidth shou ld be <500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter. table 9. gtx_clk125 ac timing specifications at recommended operating conditions with lv dd = 2.5 0.125 mv/ 3.3 v 165 mv parameter/condition symbol min typical max unit notes gtx_clk125 frequency t g125 ?1 2 5?m h z? gtx_clk125 cycle time t g125 ?8?n s?
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 16 freescale semiconductor reset dc electrical characteristics 5 reset initialization this section describes the dc and ac electrical specifications for the reset initia lization timing and el ectrical requirements of the mpc8360e/58e. 5.1 reset dc electrical characteristics this table provides the dc electrical characteris tics for the reset pins of the device. gtx_clk rise and fall time lv dd = 2.5 v lv dd = 3.3 v t g125r /t g125f ?? 0.75 1.0 ns 1 gtx_clk125 duty cycle gmii & tbi 1000base-t for rgmii & rtbi t g125h /t g125 45 47 ? 55 53 % 2 gtx_clk125 jitter ? ? ? 150 ps 2 notes: 1. rise and fall times for gtx_clk125 are measured from 0.5 and 2.0 v for lv dd = 2.5 v and from 0.6 and 2.7 v for lv dd =3.3v. 2. gtx_clk125 is used to generate the gtx clock for the ucc ethernet transmitter with 2% de gradation. the gtx_clk125 duty cycle can be loosened from 47%/53% as long as the ph y device can tolerate the duty cycle generated by gtx_clk. see section 8.2.2, ?mii ac timing specifications ,? section 8.2.3, ?rmii ac timing specifications ,? and section 8.2.5, ?rgmii and rtbi ac timing specifications? for the duty cycle for 10base-t and 100base-t reference clock. table 10. reset pins dc electrical ch aracteristics 1 characteristic symbol condition min max unit input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in ?? 1 0 a output high voltage v oh 2 i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applie s for pins poreset , hreset , sreset , and quiesce . 2. hreset and sreset are open drain pins, thus v oh is not relevant for those pins. table 9. gtx_clk125 ac timing specifications at recommended operating conditions with lv dd = 2.5 0.125 mv/ 3.3 v 165 mv (continued) parameter/condition symbol min typical max unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 17 reset ac electrical characteristics 5.2 reset ac electrical characteristics this section describes the ac electrical specifications for the reset initialization timing requirements of the device. this ta ble provides the reset initialization ac timing specifications for the ddr sdram component(s). this table provides the pll and dll lock times. table 11. reset initializa tion timing specifications parameter/condition min max unit notes required assertio n time of hreset or sreset (input) to activate reset flow 32 ? t pci_sync_in 1 required assertio n time of poreset with stable clock applied to clkin when the device is in pci host mode 32 ? t clkin 2 required assertio n time of poreset with stable clock applied to pci_sync_in when the device is in pci agent mode 32 ? t pci_sync_in 1 hreset /sreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to sreset negation (output) 16 ? t pci_sync_in 1 input setup time for por config signals (cfg_reset_source[0:2] and cfg_clkin_div) with respec t to negation of poreset when the device is in pci host mode 4?t clkin 2 input setup time for por config signals (cfg_reset_source[0:2] and cfg_clkin_div) with respec t to negation of poreset when the device is in pci agent mode 4?t pci_sync_in 1 input hold time for por config signals with respect to negation of hreset 0? ns ? time for the device to turn off por config signals with respect to the assertion of hreset ?4 ns 3 time for the device to turn on por config signals with respect to the negation of hreset 1?t pci_sync_in 1 , 3 notes: 1. t pci_sync_in is the clock period of the input clock applied to pc i_sync_in. when the device is in pci host mode the primary clock is applied to the clkin input, and pci_sync _in period depends on the value of cfg_clkin_div. refer mpc8360e powerquicc ii pro integrated communications processor reference manual for more details. 2. t clkin is the clock period of the input clock applied to clkin. it is only valid when the device is in pci host mode. refer mpc8360e powerquicc ii pro integrated co mmunications processor reference manual for more details. 3. por config signals consists of cfg_ reset_source[0:2] and cfg_clkin_div. table 12. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s? dll lock times 7680 122,880 csb_clk cycles 1 , 2 notes: 1. dll lock times are a function of the ra tio between the ou tput clock and the coherency syst em bus clock (csb_clk). a 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. the csb_clk is determined by the clkin and system pll ratio. see section 21, ?clocking,? for more information.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 18 freescale semiconductor quicc engine block operating frequency limitations 5.3 quicc engine block operating frequency limitations this section specify the limits of th e ac electrical characteristics for the operation of the quicc engine block?s communication interfaces. note the settings listed below are required fo r correct hardware interface operation. each protocol by itself requires a minimal quicc engine block operating frequency setting for meeting the performance target. because the pe rformance is a complex function of all the quicc engine block settings, the user should make use of the quicc engine block performance utility tool provided by freescale to validate their system. this table lists the maximal quicc engine block i/o frequencies and the minimal quicc engine block core frequency for each interface. 6 ddr and ddr2 sdram this section describes the dc and ac electrical speci fications for the ddr and ddr2 sdram interface of the mpc8360e/58e. table 13. quicc engine block operating frequency limitations interface interface operating frequency (mhz) max interface bit rate (mbps) min quicc engine operating frequency 1 (mhz) notes ethernet management: mdc/mdio 10 (max) 10 20 ? mii 25 (typ) 100 50 ? rmii 50 (typ) 100 50 ? gmii/rgmii/tbi/rtbi 125 (typ) 1000 250 ? spi (master/slave) 10 (max) 10 20 ? ucc through tdm 50 (max) 70 8 f 2 mcc 25 (max) 16.67 16 f 2 , 4 utopia l2 50 (max) 800 2 f 2 pos-phy l2 50 (max) 800 2 f 2 hdlc bus 10 (max) 10 20 ? hdlc/transparent 50 (max) 50 8/3 f 2 , 3 uart/async hdlc 3.68 (max internal ref clock) 115 (kbps) 20 ? bisync 2 (max) 2 20 ? usb 48 (ref clock) 12 96 ? notes: 1. the quicc engine module needs to run at a frequency higher than or equal to what is listed in this table. 2. ?f? is the actual interface operating frequency.\ 3. the bit rate limit is independent of the data bus width (t hat is, the same for serial, nibble, or octal interfaces). 4. tdm in high-speed mode for serial data interface.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 19 ddr and ddr2 sdram dc electrical characteristics 6.1 ddr and ddr2 sdram dc electrical characteristics this table provides the recommended operating conditions for the ddr2 sdra m component(s) of the device when gv dd (typ) = 1.8 v. this table provides the ddr2 capacitance when gv dd (typ) = 1.8 v. this table provides the recommende d operating conditions for the ddr sdram component(s) of the device when gv dd (typ) = 2.5 v. table 14. ddr2 sdram dc electr ical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v 2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.125 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.125 v ? output leakage current i oz ? 1 0 a 4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? mv ref input leakage current i vref ? 1 0 a? input current (0 v v in ov dd )i in ? 1 0 a? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to equal 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref cannot exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to wh ich far end signal termination is made and is expected to equal mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 15. ddr2 sdram capacitance for gv dd (typ)=1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68p f 1 delta input/output capaci tance: dq, dqs, dqs c dio ?0 . 5p f 1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 16. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v 2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 20 freescale semiconductor ddr and ddr2 sdram ac electrical characteristics this table provides the ddr capacitance when gv dd (typ) = 2.5 v . 6.2 ddr and ddr2 sdram ac electrical characteristics this section provides the ac electrical charact eristics for the ddr and ddr2 sdram interface. 6.2.1 ddr and ddr2 sdram input ac timing specifications this table provides the input ac timing specifications for the ddr2 sdram interface when gv dd (typ) = 1.8 v. input high voltage v ih mv ref + 0.18 gv dd + 0.3 v ? input low voltage v il ?0.3 mv ref ? 0.18 v ? output leakage current i oz ? 1 0 a 4 output high current (v out = 1.95 v) i oh ?15.2 ? ma ? output low current (v out = 0.35 v) i ol 15.2 ? ma ? mv ref input leakage current i vref ? 1 0 a? input current (0 v v in ov dd )i in ? 1 0 a? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 17. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68p f 1 delta input/output ca pacitance: dq, dqs c dio ?0 . 5p f 1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 18. ddr2 sdram input ac timing specifications for gv dd (typ) = 1.8 v at recommended operating conditions with gv dd of 1.8 v 5%. parameter symbol min max unit notes ac input low voltage v il ?m v ref ? 0.25 v ? ac input high voltage v ih mv ref + 0.25 ? v ? table 16. ddr sdram dc electr ical characte ristics for gv dd (typ) = 2.5 v (continued) parameter/condition symbol min max unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 21 ddr and ddr2 sdram ac electrical characteristics this table provides the input ac timing specifications for the ddr sdram interface when gv dd (typ) = 2.5 v . this figure shows the input timing diagram for the ddr controller. figure 6. ddr input timing diagram table 19. ddr sdram input ac timing specifications at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol min max unit notes ac input low voltage v il ?m v ref ? 0.31 v ? ac input high voltage v ih mv ref + 0.31 ? v ? table 20. ddr and ddr2 sdram input ac timing specifications mode at recommended operating conditions with gv dd of (1.8 or 2.5 v) 5%. parameter symbol min max unit notes mdqs?mdq/mecc input skew per byte 333 mhz 266 mhz 200 mhz t diskew ?750 ?1125 ?1250 750 1125 1250 ps 1 , 2 notes: 1. ac timing values are based on the ddr data ra te, which is twice the ddr memory bus frequency. 2. maximum possible skew between a data strobe (mdqs[n]) and any corresponding bit of data (mdq[8n + {0...7}] if 0 n 7) or ecc (mecc[{0...7}] if n = 8). mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 22 freescale semiconductor ddr and ddr2 sdram ac electrical characteristics 6.2.2 ddr and ddr2 sdram outp ut ac timing specifications table 21 and table 22 provide the output ac timing specifications a nd measurement conditions for the ddr and ddr2 sdram interface. table 21. ddr and ddr2 sdram output ac timing specifications for source synchronous mode at recommended operating conditions with gv dd of (1.8 v or 2.5 v) 5%. parameter 8 symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) t mck 61 0n s 2 skew between any mck to addr/cmd 333 mhz 266 mhz 200 mhz t aoskew ?1.0 ?1.1 ?1.2 0.2 0.3 0.4 ns 3 addr/cmd output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhas 2.1 2.8 3.5 ?ns 4 addr/cmd output hold with respect to mck 333 mhz 266 mhz?ddr1 266 mhz?ddr2 200 mhz t ddkhax 2.0 2.7 2.8 3.5 ?n s 4 mcs (n) output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcs 2.1 2.8 3.5 ?ns 4 mcs (n) output hold with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcx 2.0 2.7 3.5 ?ns 4 mck to mdqs t ddkhmh ?0.8 0.7 ns 5 , 9 mdq/mecc/mdm output setup with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhds , t ddklds 0.7 1.0 1.2 ?ns 6 mdq/mecc/mdm output hold with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhdx , t ddkldx 0.7 1.0 1.2 ?ns 6 mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck + 0.6 ns 7
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 23 ddr and ddr2 sdram ac electrical characteristics this figure shows the ddr sdram output timing for address skew with respect to any mck. figure 7. timing diagram for t aoskew measurement mdqs epilogue end t ddkhme ?0.6 0.9 ns 7 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. in the source synchronous mode, mck/mck can be shifted in ? applied cycle increm ents through the clock control register. for the skew measurements referenced for t aoskew it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of mck. 4. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. for the addr/cmd setup and hold specificat ions, it is assumed that the clock control re gister is set to adjust the memory clocks by ? applied cycle. 5. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) cloc k (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 regist er. in source synchronous mode, this is typically set to the same delay as the clock adjust in the clk_cntl register. the ti ming parameters listed in the table assume that these two parameters have been set to the same adjustment value. refer mpc8360e powerquicc ii pro integrated communications processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 6. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data stro be should be centered inside of the data eye at the pins of the device. 7. all outputs are referenced to the rising edge of mck(n) at the pins of the device. note that t ddkhmp follows the symbol conventions described in note 1. 8. ac timing values are based on the ddr data ra te, which is twice the ddr memory bus frequency. 9. in rev. 2.0 silicon, t ddkhmh maximum meets the s pecification of 0.6 ns. in rev. 2.0 silicon, due to errata, t ddkhmh minimum is ?0.9 ns. refer to errata ddr18 in chip errata for the mpc8360e, rev. 1 . table 21. ddr and ddr2 sdram output ac timing specifications for source synchronous mode (continued) at recommended operating conditions with gv dd of (1.8 v or 2.5 v) 5%. parameter 8 symbol 1 min max unit notes addr/cmd mck [n] mck[n] t mck cmd noop t aoskew(min) addr/cmd cmd noop t aoskew(max)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 24 freescale semiconductor ddr and ddr2 sdram ac electrical characteristics this figure provides the ac test load for the ddr bus. figure 8. ddr ac test load this figure shows the ddr sdram output timing diagram for source synchronous mode. figure 9. ddr sdram output timing diagram for source synchronous mode table 22. ddr and ddr2 sdram measurement conditions symbol ddr ddr2 unit notes v th mv ref 0.31 v mv ref 0.25 v v 1 v out 0.5 gv dd 0.5 gv dd v 2 notes: 1. data input threshold measurement point. 2. data output measurement point. output z 0 = 50 gv dd /2 r l = 50 addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 write a0 noop t ddkhme t ddkhmp t ddkhax , t ddkhcx
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 25 duart dc electrical characteristics 7duart this section describes the dc and ac electrical speci fications for the duart interface of the mpc8360e/58e. 7.1 duart dc electrical characteristics this table provides the dc electrical characteris tics for the duart interface of the device. 7.2 duart ac electrical specifications this table provides the ac timing parame ters for the duart interface of the device. 8 ucc ethernet controller: three-speed ethernet, mii management this section provides the ac and dc electrical characteristics for three-speed, 10/100/1000, and mii management. 8.1 three-speed ethernet co ntroller (10/100/1000 mbps)? gmii/mii/rmii/tbi/rgmii/rtbi electrical characteristics the electrical characteristics sp ecified here apply to all gmii (gigabit medi a independent interface), mii (media independent interface), rmii (reduced media independent interface), tbi (t en-bit interface), rgmii (redu ced gigabit media independent interface), and rtbi (reduced ten-bit interface) signals excep t mdio (management data input /output) and md c (management data clock). the mii, rmii, gmii, and tbi interfaces are only de fined for 3.3 v, while the rgmii and rtbi interfaces are only defined for 2.5 v. the rgmii and rtbi interfaces follow the hewl ett-packard reduced pin-count interface for gigabit ethernet table 23. duart dc electrical characteristics parameter symbol min max unit notes high-level input voltage v ih 2ov dd + 0.3 v ? low-level input voltage ov dd v il ?0.3 0.8 v ? high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v ? low-level output voltage, i ol = 100 av ol ?0 . 2v? input current (0 v v in ov dd )i in ? 1 0 a 1 note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta bl e 2 . table 24. duart ac timing specifications parameter value unit notes minimum baud rate 256 baud ? maximum baud rate >1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate is limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the eighth sampl ed 0 after the 1-to-0 transition of the start bit. subsequent bit va lues are sampled each sixteenth sample.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 26 freescale semiconductor gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications physical layer device specification version 1.2a (9/22/2000) . the electrical characteristics for the mdio and mdc are specified in section 8.3, ?ethernet management interface electrical characteristics.? 8.1.1 10/100/1000 ethernet dc electrical characteristics the electrical characteristics specified he re apply to media independent interface (m ii), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), reduced me dia independent interface (rmii) signals, management data input/output (mdio) and management data clock (mdc). the mii and rmii interfaces are defined for 3.3 v, while the rgmii and rtbi interfaces can be operated at 2.5 v. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3. the rmii interface follows the rmii consortium rmii specification version 1.2. 8.2 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications the ac timing specifications for gmii, mii, tbi, rgmii, and rtbi are presented in this section. 8.2.1 gmii timing specifications this sections describe the gmii transm it and receive ac timing specifications. table 25. rgmii/rtbi, gmii, tbi, mii, and rmii dc electrical characteristics (when operating at 3.3 v) parameter symbol conditions min max unit notes supply voltage 3.3 v lv dd ? 2.97 3.63 v 1 output high voltage v oh i oh = ?4.0 ma lv dd = min 2.40 lv dd + 0.3 v ? output low voltage v ol i ol = 4.0 ma lv dd = min gnd 0.50 v ? input high voltage v ih ??2 . 0l v dd + 0.3 v ? input low voltage v il ? ? ?0.3 0.90 v ? input current i in 0 v v in lv dd ? 1 0 a? note: 1. gmii/mii pins that are not needed for rgmii, rmii, or rtbi operation are powered by the ov dd supply. table 26. rgmii/rtbi dc electrical characteristics (when operating at 2.5 v) parameters symbol conditions min max unit supply voltage 2.5 v lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd ? 0.3 0.40 v input high voltage v ih ?l v dd = min 1.7 lv dd + 0.3 v input low voltage v il ?l v dd = min ?0.3 0.70 v input current i in 0 v v in lv dd ? 1 0 a
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 27 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.1.1 gmii transmit ac timing specifications this table provides the gmii transmit ac timing specifications. this figure shows the gmii transmit ac timing diagram. figure 10. gmii transmit ac timing diagram table 27. gmii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t gtx ?8.0?ns? gtx_clk duty cycle t gtxh/tgtx 40 ? 60 % ? gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx t gtkhdv 0.5 ? ?? 5.0 ns 3 gtx_clk clock rise time, (20% to 80%) t gtxr ??1.0ns? gtx_clk clock fall time, (80% to 20%) t gtxf ??1.0ns? gtx_clk125 clock period t g125 ?8.0?ns 2 gtx_clk125 reference clock duty cycle measured at lv dd/2 t g125h /t g125 45 ? 55 % 2 notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. fo r example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with th e appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 signal and does not follow the original symbol naming convention. 3. in rev. 2.0 silicon, due to errata, t gtkhdx minimum and t gtkhdv maximum are not supported when the gtx_clk is selected. refer to errata qe_enet18 in chip errata for the mpc8360e, rev. 1 . gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf tx_en tx_er
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 28 freescale semiconductor gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.1.2 gmii receive ac timing specifications this table provides the gmii r eceive ac timing specifications. this figure shows the gmii receive ac timing diagram. figure 11. gmii receive ac timing diagram table 28. gmii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes rx_clk clock period t grx ?8.0?ns? rx_clk duty cycle t grxh /t grx 40 ? 60 % ? rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns ? rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.2 ? ? ns 2 rx_clk clock rise time, (20% to 80%) t grxr ??1.0ns? rx_clk clock fall time, (80% to 20%) t grxf ??1.0ns? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input si gnals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representat ion is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. in rev. 2.0 silicon, due to errata, t grdxkh minimum is 0.5 which is not compliant with the standard. refer to errata qe_enet18 in chip errata for the mpc8360e, rev. 1 . rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 29 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.2 mii ac timing specifications this section describes the mii transmit and receive ac tim ing specifications. 8.2.2.1 mii transmit ac timing specifications this table provides the mii transmit ac timing specifications. this figure shows the mii transmit ac timing diagram. figure 12. mii transmit ac timing diagram table 29. mii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh /t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx t mtkhdv 1 ? 5? 15 ns tx_clk data clock rise time, (20% to 80%) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall time, (80% to 20%) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data out puts (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to th ree letters representing the cl ock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 30 freescale semiconductor gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.2.2 mii receive ac timing specifications this table provides the mii r eceive ac timing specifications. this figure provides the ac test load. figure 13. ac test load this figure shows the mii receive ac timing diagram. figure 14. mii receive ac timing diagram table 30. mii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise time, (20% to 80%) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time, (80% to 20%) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input sign als (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the cl ock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 31 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.3 rmii ac timing specifications this section describes the rmii trans mit and receive ac timing specifications. 8.2.3.1 rmii transmit ac timing specifications this table provides the rmii transmit ac timing specifications. this figure shows the rmii transmit ac timing diagram. figure 15. rmii transmit ac timing diagram 8.2.3.2 rmii receive ac timing specifications this table provides the rmii receive ac timing specifications. table 31. rmii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit ref_clk clock t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk to rmii data txd[1:0], tx_en delay t rmtkhdx t rmtkhdv 2 ? ?? 10 ns ref_clk data clock rise time t rmxr 1.0 ? 4.0 ns ref_clk data clock fall time t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t rmtkhdx symbolizes rmii transmit timing (rmt) for the time t rmx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii(rm) reference (x) cloc k. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 32. rmii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit ref_clk clock period t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk txd[1:0] t rmtkhdx t rmx t rmxh t rmxr t rmxf tx_en
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 32 freescale semiconductor gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications this figure provides the ac test load. figure 16. ac test load this figure shows the rmii receive ac timing diagram. figure 17. rmii receive ac timing diagram 8.2.4 tbi ac timing specifications this section describes the tbi transmit and receive ac timing specifications. rxd[1:0], crs_dv, rx_er setup time to ref_clk t rmrdvkh 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk t rmrdxkh 2.0 ? ? ns ref_clk clock rise time t rmxr 1.0 ? 4.0 ns ref_clk clock fall time t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t rmrdvkh symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) reach the valid state (v) relative to the t rmx clock reference (k) going to the high (h) state or setup time. also, t rmrdxkl symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) went invalid (x) relative to the t rmx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol represen tation is based on three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii (rm) reference (x) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 32. rmii receive ac timing specifications (continued) at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit output z 0 = 50 lv dd /2 r l = 50 ref_clk rxd[1:0] t rmrdxkh t rmx t rmxh t rmxr t rmxf crs_dv rx_er t rmrdvkh valid data
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 33 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.4.1 tbi transmit ac timing specifications this table provides the tbi transmit ac timing specifications. this figure shows the tbi transmit ac timing diagram. figure 18. tbi transmit ac timing diagram table 33. tbi transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes gtx_clk clock period t ttx ?8.0?ns? gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % ? gtx_clk to tbi data tcg[9:0] delay t ttkhdx t ttkhdv 1.0 ? ?? 5.0 ns 3 gtx_clk clock rise time, (20% to 80%) t ttxr ??1.0ns? gtx_clk clock fall time, (80% to 20%) t ttxf ??1.0ns? gtx_clk125 reference clock period t g125 ?8.0?ns 2 gtx_clk125 reference clock duty cycle t g125h /t g125 45 ? 55 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid st ate (x) or hold time. note that, in general, the clock refer ence symbol representation is based on three lett ers representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 and does not follow the original symbol naming convention. 3. in rev. 2.0 silicon, due to errata, t ttkhdx minimum is 0.7 ns for ucc1. refer to errata qe_enet19 in chip errata for the mpc8360e, rev. 1 . gtx_clk txd[7:0] t ttx t ttxh t ttxr t ttxf t ttkhdx tx_en tx_er
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 34 freescale semiconductor gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.4.2 tbi receive ac timing specifications this table provides the tbi r eceive ac timing specifications. this figure shows the tbi receive ac timing diagram. figure 19. tbi receive ac timing diagram table 34. tbi receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes pma_rx_clk clock period t trx ? 16.0 ? ns ? pma_rx_clk skew t sktrx 7.5 ? 8.5 ns ? rx_clk duty cycle t trxh /t trx 40 ? 60 % ? rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns 2 rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.0 ? ? ns 2 rx_clk clock rise time, v il (min) to v ih (max) t trxr 0.7 ? 2.4 ns ? rx_clk clock fall time, v ih (max) to v il (min) t trxf 0.7 ? 2.4 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signal s (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three le tters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for ri se and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols re presenting skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. setup and hold time of even number ed rcg are measured from riding edge of pma_rx_clk1. setup and hold time of odd numbered rcg are measured from riding edge of pma_rx_clk0. pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh even rcg odd rcg
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 35 gmii, mii, rmii, tbi, rgmii, and rtbi ac timing specifications 8.2.5 rgmii and rtbi ac timing specifications this table presents the rgmii a nd rtbi ac timing specifications. table 35. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes data to clock output skew (at transmitter) t skrgtkhdx t skrgtkhdv ?0.5 ? ?? 0.5 ns 7 data to clock input skew (at receiver) t skrgdxkh t skrgdvkh 1.0 ? ?? 2.6 ns 2 clock cycle duration t rgt 7.2 8.0 8.8 ns 3 duty cycle for 1000base-t t rgth /t rgt 45 50 55 % 4 , 5 duty cycle for 10base-t and 100base-tx t rgth /t rgt 40 50 60 % 3 , 5 rise time (20?80%) t rgtr ? ? 0.75 ns ? fall time (20?80%) t rgtf ? ? 0.75 ns ? gtx_clk125 reference clock period t g125 ?8.0?ns 6 gtx_clk125 reference clock duty cycle t g125h /t g125 47 ? 53 % ? notes: 1. note that, in general, the clock reference symbol representati on for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (r x) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. fo r symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns can be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. duty cycle reference is lv dd /2. 6. this symbol is used to represent the external gtx_clk 125 and does not follow the original symbol naming convention. 7. in rev. 2.0 silicon, due to errata, t skrgtkhdx minimum is ?2.3 ns and t skrgtkhdv maximum is 1 ns for ucc1, 1.2 ns for ucc2 option 1, and 1.8 ns for ucc2 option 2. in rev. 2.1 silicon, due to errata, t skrgtkhdx minimum is ?0.65 ns for ucc2 option 1 and ?0.9 for ucc2 option 2, and t skrgtkhdv maximum is 0.75 ns for ucc1 and ucc2 option 1 and 0.85 for ucc2 option 2. refer to errata qe_enet10 in chip errata for the mpc8360e, rev. 1 . ucc1 does meet t skrgtkhdx minimum for rev. 2.1 silicon.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 36 freescale semiconductor ethernet management interface electrical characteristics this figure shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 20. rgmii and rtbi ac timing and multiplexing diagrams 8.3 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interf ace signals mdio (managem ent data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, tbi, and rtbi are specified in section 8.1, ?three-speed ethernet c ontroller (10/100/1000 mbps)? gmii/mii/rmii/tbi/rgmii/rtbi electrical characteristics.? 8.3.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in this table. table 36. mii management dc electrical characteristics when powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) ov dd ? 2.97 3.63 v output high voltage v oh i oh = ?1.0 ma ov dd = min 2.10 ov dd + 0.3 v output low voltage v ol i ol = 1.0 ma ov dd = min gnd 0.50 v input high voltage v ih ?2 . 0 0?v input low voltage v il ? ? 0.80 v input current i in 0 v v in ov dd ? 1 0 a gtx_clk t rgt t rgth t skrgtkhdx tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgtkhdx t skrgtkhdx t skrgtkhdx
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 37 ethernet management interface electrical characteristics 8.3.2 mii management ac electrical specifications this table provides the mii management ac timing specifications. this figure shows the mii management ac timing diagram. figure 21. mii management interface timing diagram table 37. mii management ac timing specifications at recommended operating conditions with lv dd is 3.3 v 10%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc ?2 . 5?m h z 2 mdc period t mdc ?4 0 0?n s? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio delay t mdtkhdx t mdtkhdv 10 ? ?? 110 ns 3 mdio to mdc setup time t mdrdvkh 10 ? ? ns ? mdio to mdc hold time t mdrdxkh 0??n s? mdc rise time t mdcr ? ? 10 ns ? mdc fall time t mdhf ? ? 10 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mdrdvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with th e appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; fo r a csb_clk of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz). 3. this parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 mhz, the delay is 90 ns and for a ce_clk of 300 mhz, the delay is 63 ns). mdc t mdrdxkh t mdc t mdch t mdcr t mdhf t mdtkhdx mdio mdio (input) (output) t mdrdvkh
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 38 freescale semiconductor local bus dc electrical characteristics 8.3.3 ieee 1588 timer ac specifications this table provides the ieee 1588 timer ac specifications. 9 local bus this section describes the dc and ac electrical specifi cations for the local bus in terface of the mpc8360e/58e. 9.1 local bus dc electrical characteristics this table provides the dc electrical characteristics for the local bus interface. 9.2 local bus ac electrical specifications this table describes the general timing parame ters of the local bus interface of the device. table 38. ieee 1588 timer ac specifications parameter symbol min max unit notes timer clock frequency t tmrck 070mhz 1 input setup to timer clock t tmrcks ??? 2 , 3 input hold from timer clock t tmrckh ??? 2 , 3 output clock to output valid t gclknv 06ns? timer alarm to output valid t tmral ??? 2 notes: 1. the timer can operate on rtc_clock or tmr_clock. thes e clocks get muxed and any one of them can be selected. the minimum and maximum requirement for both rtc_clock and tmr_clock are the same. 2. these are asynchronous signals. 3. inputs need to be stable at least one tmr clock. table 39. local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2o v dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v low-level output voltage, i ol = 100 av ol ?0 . 2v input current i in ? 1 0 a table 40. local bus general timing parameters?dll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 ? ns 2 input setup to local bus clock (except lupwait) t lbivkh1 1.7 ? ns 3 , 4 lupwait input setup to local bus clock t lbivkh2 1.9 ? ns 3 , 4 input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns 3 , 4
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 39 local bus ac electrical specifications this table describes the general timing parame ters of the local bus interface of the device. lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3 , 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3.0 ? ns 6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to lale rise t lbkhlr ?4.5ns ? local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?4.5ns ? local bus clock to data valid for lad/ldp t lbkhov2 ?4.5ns 3 local bus clock to address valid for lad t lbkhov3 ?4.5ns 3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 1.0 ? ns 3 output hold from local bus clock for lad/ldp t lbkhox2 1.0 ? ns 3 local bus clock to output high impedance for lad/ldp t lbkhoz ?3.8ns 8 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to rising edge of lsync_in. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing meas urements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. table 41. local bus general timing parameters?dll bypass mode 9 parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to lo cal bus clock t lbivkh 7?ns 3 , 4 input hold from local bus clock t lbixkh 1.0 ? ns 3 , 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns 6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 table 40. local bus general timing parameters?dll enabled (continued) parameter symbol 1 min max unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 40 freescale semiconductor local bus ac electrical specifications this figure provides the ac test load for the local bus. figure 22. local bus c test load local bus clock to output valid t lbkhov ?3ns 3 local bus clock to output high impedance for lad/ldp t lbkhoz ?4ns 8 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10 pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing meas urements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 9. dll bypass mode is not recommended for use at frequencies above 66 mhz. table 41. local bus general timing parameters?dll bypass mode 9 (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 41 local bus ac electrical specifications these figures show the local bus signals. figure 23. local bus signals, nons pecial signals only (dll enabled) figure 24. local bus signals, nonspecial signals only (dll bypass mode) output signals: la[27:31]/lbct l/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov t lbkhov lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh t lbivkh t lbixkh t lbkhox t lbkhox t lbkhoz t lbkhlr t lbotot t lbkhoz t lbkhox output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov lclk[n] input signals: lad[0:31]/ldp[0:3] output signals: lad[0:31]/ldp[0:3] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 42 freescale semiconductor local bus ac electrical specifications figure 25. local bus signals, gpcm/upm si gnals for lcrr[clkdiv] = 2 (dll enabled) figure 26. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 (dll bypass mode) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz (dll bypass mode)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 43 local bus ac electrical specifications figure 27. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 4 (dll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 44 freescale semiconductor jtag dc electrical characteristics figure 28. local bus signals, gpcm/upm si gnals for lcrr[clkdiv] = 4 (dll enabled) 10 jtag this section describes the dc and ac electrical specifications for the ieee 1149.1 (jtag) interface of the mpc8360e/58e. 10.1 jtag dc electrical characteristics this table provides the dc electri cal characteristics for th e ieee 1149.1 (jtag) interface of the device. table 42. jtag interface dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2 . 5o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 45 jtag ac electrical characteristics 10.2 jtag ac electrical characteristics this section describes the ac electrical specificat ions for the ieee 1149.1 (jtag) interface of the device. this table provides the jtag ac timing specifications as defined in figure 30 through figure 33 . table 43. jtag ac timing specifications (independent of clkin) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock duty cycle t jtkhkl /t jtg 45 55 % ? jtag external clock rise and fall times t jtgr & t jtgf 02n s? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5 , 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are meas ured at the pins. all output timings assume a purely resistive 50- load (see figure 22 ). time-of-flight delays must be added for tr ace lengths, vias, and connectors in the system. 2. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time dat a input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 46 freescale semiconductor jtag ac electrical characteristics this figure provides the ac test load for tdo an d the boundary-scan outputs of the device. figure 29. ac test load for the jtag interface this figure provides the jtag clock input timing diagram. figure 30. jtag clock input timing diagram this figure provides the trst timing diagram. figure 31. trst timing diagram this figure provides the boundary-scan timing diagram. figure 32. boundary-scan timing diagram output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 47 i2c dc electrical characteristics this figure provides the test access port timing diagram. figure 33. test access port timing diagram 11 i 2 c this section describes the dc and ac electrical character istics for the i 2 c interface of th e mpc8360e/58e. 11.1 i 2 c dc electrical characteristics this table provides the dc el ectrical character istics for the i 2 c interface of the device. table 44. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 10%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00 . 4v 1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which mu st be suppressed by the input filter t i2khkl 05 0n s 3 capacitance for each i/o pin c i ?1 0p f? input current (0 v v in ov dd )i in ? 1 0 a 4 notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8360e integrated communications processor reference manual for information on the digital filter used. 4. i/o pins obstruct the sda and scl lines if ov dd is switched off. vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 48 freescale semiconductor i2c ac electrical specifications 11.2 i 2 c ac electrical specifications this table provides the ac timing parameters for the i 2 c interface of the device. table 45. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta bl e 4 4 ). parameter symbol 1 min max unit note scl clock frequency f i2c 0 400 khz 2 low period of the scl clock t i2cl 1.3 ? s? high period of the scl clock t i2ch 0.6 ? s? setup time for a repeated start condition t i2svkh 0.6 ? s? hold time (repeated) start cond ition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s? data setup time t i2dvkh 100 ? ns 3 data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s? rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns ? fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns ? set-up time for stop condition t i2pvkh 0.6 ? s? bus free time between a stop and start condition t i2khdx 1.3 ? s? noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v? noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) re aching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall time s, the latter convention is us ed with the appropriate letter: r (rise) or f (fall). 2. the device provides a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 49 pci dc electrical characteristics this figure provides the ac test load for the i 2 c. figure 34. i 2 c ac test load this figure shows the ac timing diagram for the i 2 c bus. figure 35. i 2 c bus ac timing diagram 12 pci this section describes the dc and ac electrical sp ecifications for the pci bu s of the mpc8360e/58e. 12.1 pci dc electrical characteristics this table provides the dc electrical characteris tics for the pci interface of the device. 12.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the device. note th at the pci_clk or pci_sync_in signal is used as the pci input clock depending on whether the de vice is configured as a host or agent device. this table provi des the pci ac timing specifications at 66 mhz. . table 46. pci dc electrical characteristics parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 0.5 ov dd ov dd + 0.5 v low-level input voltage v il v out v ol (max) -0.5 0.3 ov dd v high-level output voltage v oh i oh = ?500 a0.9 ov dd ?v low-level output voltage v ol i ol = 1500 a ? 0.1 ov dd v input current i in 0 v v in 1 ov dd ? 1 0 a table 47. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?6 . 0n s 2 , 5 output hold from clock t pckhox 1?n s 2 output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 50 freescale semiconductor pci ac electrical specifications this figure provides the ac test load for pci. figure 36. pci ac test load clock to output high impedance t pckhoz ?1 4n s 2 , 3 input setup to clock t pcivkh 3.0 ? ns 2 , 4 input hold from clock t pcixkh 0.3 ? ns 2 , 4 , 6 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing meas urements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 4. input timings are measured at the pin. 5. in rev. 2.0 silicon, due to errata, t pcihov maximum is 6.6 ns. refer to errata pci21 in chip errata for the mpc8360e, rev. 1 . 6. in rev. 2.0 silicon, due to errata, t pcixkh minimum is 1 ns. refer to errata pci17 in chip errata for the mpc8360e, rev. 1 . table 48. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?1 1n s 2 output hold from clock t pckhox 2?n s 2 clock to output high impedance t pckhoz ?1 4n s 2 , 3 input setup to clock t pcivkh 7.0 ? ns 2 , 2 input hold from clock t pcixkh 0.3 ? ns 2 , 4 , 5 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) r each the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing meas urements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 4. input timings are measured at the pin. 5. in rev. 2.0 silicon, due to errata, t pcixkh minimum is 1 ns. refer to errata pci17 in chip errata for the mpc8360e, rev. 1 . table 47. pci ac timing specifications at 66 mhz (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 51 timers dc electrical characteristics this figure shows the pci input ac timing conditions. figure 37. pci input ac timing measurement conditions this figure shows the pci output ac timing conditions. figure 38. pci output ac timing measurement condition 13 timers this section describes the dc and ac electrical specifications for the timers of the mpc8360e/58e. 13.1 timers dc electrical characteristics this table provides the dc elect rical characteristics fo r the device timer pins, including tin, tout , tgate , and rtc_clk. table 49. timers dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 52 freescale semiconductor timers ac timing specifications 13.2 timers ac timing specifications this table provides the timer input and output ac timing specifications. this figure provides the ac test load for the timers. figure 39. timers ac test load 14 gpio this section describes the dc and ac electrical specifications for the gpio of the mpc8360e/58e. 14.1 gpio dc electrical characteristics this table provides the dc electrical characteristics fo r the device gpio. table 50. timers input ac timing specifications 1 characteristic symbol 2 typ unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. timers inputs and outputs are asynchronous to any visible cl ock. timers outputs should be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation. table 51. gpio dc electrical characteristics characteristic symbol condition min max unit notes output high voltage v oh i oh = ?6.0 ma 2.4 ? v 1 output low voltage v ol i ol = 6.0 ma ? 0.5 v 1 output low voltage v ol i ol = 3.2 ma ? 0.4 v 1 input high voltage v ih ?2 . 0o v dd + 0.3 v 1 input low voltage v il ?? 0 . 30 . 8v? input current i in 0 v v in ov dd ? 1 0 a? note: 1. this specification applies w hen operating from 3.3-v supply. output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 53 gpio ac timing specifications 14.2 gpio ac timing specifications this table provides the gpio input and output ac timing specifications. this figure provides the ac test load for the gpio. figure 40. gpio ac test load 15 ipic this section describes the dc and ac electrical specificatio ns for the external interrupt pins of the mpc8360e/58e. 15.1 ipic dc electrical characteristics this table provides the dc elect rical characteristics for the external interrupt pins of the ipic. table 52. gpio input ac timing specifications 1 characteristic symbol 2 typ unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible cloc k. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. table 53. ipic dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in ?? 1 0 a output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq [0:7], irq_out , mcp_out , and ce ports interrupts. 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 54 freescale semiconductor ipic ac timing specifications 15.2 ipic ac timing specifications this table provides the ipic input and output ac timing specifications. 16 spi this section describes the dc and ac electrical specifications for the spi of the mpc8360e/58e. 16.1 spi dc electrical characteristics this table provides the dc electri cal characteristics for the device spi. 16.2 spi ac timing specifications this table and provide the spi input and output ac timing specifications. table 54. ipic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode. table 55. spi dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?6.0 ma 2.4 ? v output low voltage v ol i ol = 6.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a table 56. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs?master mode (internal clock) delay t nikhox t nikhov 0.3 ? ? 8 ns spi outputs?slave mode (external clock) delay t nekhox t nekhov 2 ? ? 8 ns spi inputs?master mode (interna l clock) input setup time t niivkh 8?ns spi inputs?master mode (internal clock) input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 55 spi ac timing specifications this figure provides the ac test load for the spi. figure 41. spi ac test load these figures represent the ac timing from table 56 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also a pply when the falling edge is the active edge. this figure shows the spi timing in slave mode (external clock). figure 42. spi ac timing in slave mode (external clock) diagram this figure shows the spi timing in master mode (internal clock). figure 43. spi ac timing in master mode (internal clock) diagram spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t nikhov symbolizes the nmsi outputs internal timing (ni) for the time t spi memory clock reference (k) goes from the high state (h) until outputs (o) are valid (v). table 56. spi ac timing specifications 1 characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50 spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 56 freescale semiconductor tdm/si dc electrical characteristics 17 tdm/si this section describes the dc and ac electrical specifications for the time-division-multiplexed and serial interface of the mpc8360e/58e. 17.1 tdm/si dc electrical characteristics this table provides the dc electrical characteristics for the device tdm/si. 17.2 tdm/si ac timing specifications this table provides the tdm/si input and output ac timing specifications. this figure provides the ac test load for the tdm/si. figure 44. tdm/si ac test load figure 45 represents the ac timing from table 56 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also a pply when the falling edge is the active edge. table 57. tdm/si dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a table 58. tdm/si ac timing specifications 1 characteristic symbol 2 min max 3 unit tdm/si outputs?external clock delay t sekhov 21 0n s tdm/si outputs?external clock high impedance t sekhox 21 0n s tdm/si inputs?external clock input setup time t seivkh 5?n s tdm/si inputs?external clock input hold time t seixkh 2?n s notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h ) until outputs (o) are invalid (x). 3. timings are measured from the positive or negative edge of the clock, according to sixmr [ce] and sitxcei[txceix]. refer mpc8360e integrated communications processor reference manual for more details. output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 57 utopia/pos this figure shows the tdm/si timing with external clock. figure 45. tdm/si ac timing (external clock) diagram 17.3 utopia/pos this section describes the dc and ac electrical speci fications for the utopia/pos of the mpc8360e/58e. 17.4 utopia/pos dc electrical characteristics this table provides the dc electrical characteristics for the device utopia. 17.5 utopia/pos ac timing specifications this table provides the utopia input and output ac timing specifications. table 59. utopia dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a table 60. utopia ac timing specifications 1 characteristic symbol 2 min max unit notes utopia outputs?internal clock delay t uikhov 01 1 . 5n s? utopia outputs?external clock delay t uekhov 11 1 . 6n s? utopia outputs?internal clock high impedance t uikhox 08 . 0n s? utopia outputs?external clock high impedance t uekhox 11 0 . 0n s? utopia inputs?internal clock input setup time t uiivkh 6?n s? utopia inputs?external clock input setup time t ueivkh 4?n s 3 tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) t sekhox note: the clock edge is selectable on tdm/si
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 58 freescale semiconductor utopia/pos ac timing specifications this figure provides the ac test load for the utopia. figure 46. utopia ac test load these figures represent the ac timing from table 56 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also a pply when the falling edge is the active edge. this figure shows the utopia timing with external clock. figure 47. utopia ac timing (external clock) diagram utopia inputs?internal clock input hold time t uiixkh 2.4 ? ns ? utopia inputs?external clock input hold time t ueixkh 1?n s 3 notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t uikhox symbolizes the utopia outputs internal timing (ui) for the time t utopia memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). 3. in rev. 2.0 silicon, due to errata, t ueivkh minimum is 4.3 ns and t ueixkh minimum is 1.4 ns under specific conditions. refer to errata qe_upc3 in chip errata for the mpc8360e, rev. 1 . table 60. utopia ac timing specifications 1 (continued) characteristic symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 utopiaclk (input) t ueixkh t ueivkh t uekhov input signals: utopia output signals: utopia t uekhox
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 59 hdlc, bisync, transparent, and synchronous uart dc electrical characteristics this figure shows the utopia timing with internal clock. figure 48. utopia ac timing (internal clock) diagram 18 hdlc, bisync, transparent, and synchronous uart this section describes the dc and ac electrical specificat ions for the high level data link control (hdlc), bisync, transparent, and synchronous uart protocols of the mpc8360e/58e. 18.1 hdlc, bisync, transparen t, and synchronous uart dc electrical characteristics this table provides the dc electrical characteristic s for the device hdlc, bisync, tran sparent, and synchronous uart protocols. 18.2 hdlc, bisync, transparent, and synchronous uart ac timing specifications these tables provide the input and output ac timing specifications for hdlc, bis ync, transparent, and synchronous uart protocols. table 61. hdlc, bisync, transparent, and synchronous uart dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?2.0 ma 2.4 ? v output low voltage v ol i ol = 3.2 ma ? 0.5 v input high voltage v ih ?2 . 0o v dd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v v in ov dd ? 1 0 a table 62. hdlc, bisync, and tran sparent ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t hikhov 01 1 . 2n s outputs?external clock delay t hekhov 11 0 . 8n s utopiaclk (output) t uiixkh t uikhov input signals: utopia output signals: utopia t uiivkh t uikhox
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 60 freescale semiconductor hdlc, bisync, transparent, and synchronous uart ac timing specifications this figure provides the ac test load. figure 49. ac test load outputs?internal clock high impedance t hikhox -0.5 5.5 ns outputs?external clock high impedance t hekhox 18n s inputs?internal clock input setup time t hiivkh 8.5 ? ns inputs?external clock input setup time t heivkh 4?n s inputs?internal clock input hold time t hiixkh 1.4 ? ns inputs?external clock input hold time t heixkh 1?n s notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 63. synchronous uart ac timing specifications 1 characteristic symbol 2 min max unit outputs?internal clock delay t uaikhov 01 1 . 3n s outputs?external clock delay t uaekhov 11 4n s outputs?internal clock high impedance t uaikhox 01 1n s outputs?external clock high impedance t uaekhox 11 4n s inputs?internal clock input setup time t uaiivkh 6?n s inputs?external clock input setup time t uaeivkh 8?n s inputs?internal clock input hold time t uaiixkh 1?n s inputs?external clock input hold time t uaeixkh 1?n s notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 62. hdlc, bisync, and transp arent ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 61 ac test load 18.3 ac test load these figures represent the ac timing from table 62 and table 63 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams al so apply when the falling edge is the active edge. this figure shows the timing with external clock. figure 50. ac timing (external clock) diagram this figure shows the timing with internal clock. figure 51. ac timing (internal clock) diagram serial clk (input) t heixkh t heivkh t hekhov input signals : (see note) output signals: (see note) t hekhox note: the clock edge is selectable . serial clk (output) t hiixkh thikhov input signals: (see note) t hiivkh t hikhox note: the clock edge is selectable. output signals: (see note)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 62 freescale semiconductor usb dc electrical characteristics 19 usb this section provides the ac and dc electrical speci fications for the usb inte rface of the mp c8360e/58e. 19.1 usb dc electrical characteristics this table provides the dc electrical characteristics for the usb interface. 19.2 usb ac electrical specifications this table describes the general timing para meters of the usb interface of the device. this figure provide the ac test load for the usb. figure 52. usb ac test load table 64. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v high-level output voltage, i oh = ?100 av oh ov dd ? 0.4 ? v low-level output voltage, i ol = 100 av ol ?0 . 2v input current i in ? 1 0 a table 65. usb general timing parameters parameter symbol 1 min max unit notes note usb clock cycle time t usck 20.83 ? ns full speed 48 mhz ? usb clock cycle time t usck 166.67 ? ns low speed 6 mhz ? skew between txp and txn t ustspn ?5ns? 2 skew among rxp, rxn, and rxd t usrspnd ? 10 ns full speed transitions 2 skew among rxp, rxn, and rxd t usrpnd ? 100 ns low speed transitions 2 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(state)(signal) for receive signals and t (first two letters of functional block)(state)(signal) for transmit signals. for example, t usrspnd symbolizes usb timing (us) for the usb receive signals skew (rs) among rxp, rxn, and rxd (pnd). also, t ustspn symbolizes usb timing (us) for the usb transmit signals skew (ts) between txp and txn (pn). 2. skew measurements are done at ov dd /2 of the rising or falling edge of the signals. output z 0 = 50 ov dd /2 r l = 50
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 63 package parameters for the tbga package 20 package and pin listings this section details package parameters, pin assignments, and dime nsions. the mpc8360e/58e is available in a tape ball grid array (tbga), see section 20.1, ?package parameters for the tbga package,? and section 20.2, ?mechanical dimensions of the tbga package,? for information on the package. 20.1 package parameters for the tbga package the package parameters for rev. 2.0 silicon are as prov ided in the following list. the package type is 37.5 mm 37.5 mm, 740 tape ball grid array (tbga). package outline 37.5 mm 37.5 mm interconnects 740 pitch 1.00 mm module height (typical) 1.46 mm solder balls 62 sn/36 pb/2 ag (zu package) 95.5 sn/0.5 cu/4 ag (vv package) ball diameter (typical) 0.64 mm
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 64 freescale semiconductor mechanical dimensions of the tbga package 20.2 mechanical dimensions of the tbga package this figure depicts the mechanical dimensions and bottom surface nomenclat ure of the device, 740-tbga package. figure 53. mechanical dimensions and bottom surface nomenclature of the tbga package
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 65 pinout listings 20.3 pinout listings refer to an3097, ?mpc8360/mpc8358e powerquicc design checklist,? for proper pin termination and usage. this table shows the pin list of the mpc8360e tbga package. table 66. mpc8360e tbga pinout listing signal package pin number pin type power supply notes primary ddr sdram memory controller interface memc1_mdq[0:31] aj34, ak33, al 33, al35, aj33, ak34, ak32, am36, an37, an35, ar34, at34, ap37, ap36, ar36, at35, ap34, ar32, ap32, am31, an33, am34, am33, am30, ap31, am27, ar30, at32, an29, ap29, an27, ar29 i/o gv dd ? memc1_mdq[32:63]/ memc2_mdq[0:31] an8, an7, am8, am6, ap9, an9, at7, ap7, au6, ap6, ar4, ar3, at6, at5, ar5, at3, ap4, am5, ap3, an3, an5, al5, an4, am2, al2, ah5, ak3, aj2, aj3, ah4, ak4, ah3 i/o gv dd ? memc1_mecc[0:4]/ msrcid[0:4] ap24, an22, am19, an19, am24 i/o gv dd ? memc1_mecc[5]/ mdval am23 i/o gv dd ? memc1_mecc[6:7] am22, an18 i/o gv dd ? memc1_mdm[0:3] al36, an34, ap33, an28 o gv dd ? memc1_mdm[4:7]/ memc2_mdm[0:3] at9, au4, am3, aj6 o gv dd ? memc1_mdm[8] ap27 o gv dd ? memc1_mdqs[0:3] ak35, ap35, an31, am26 i/o gv dd ? memc1_mdqs[4:7]/ memc2_mdqs[0:3] at8, au3, al4, aj5 i/o gv dd ? memc1_mdqs[8] ap26 i/o gv dd ? memc1_mba[0:1] au29, au30 o gv dd ? memc1_mba[2] at30 o gv dd ? memc1_ma[0:14] au21, ap22, ap21, at21, au25, au26, at23, ar26, au24, ar23, ar28, au23, ar22, au20, ar18 ogv dd ? memc1_modt[0:1] ag33, aj36 o gv dd 6 memc1_modt[2:3]/ memc2_modt[0:1] at1, ak2 o gv dd 6 memc1_mwe at 2 6 o g v dd ? memc1_mras at 2 9 o g v dd ? memc1_mcas at 2 4 o g v dd ? memc1_mcs [0:1] au27, at27 o gv dd ? memc1_mcs [2:3]/ memc2_mcs [0:1] au8, au7 o gv dd ?
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 66 freescale semiconductor pinout listings memc1_mcke[0:1] al32, au33 o gv dd 3 memc1_mck[0:1] ak37, at37 o gv dd ? memc1_mck[2:3]/ memc2_mck[0:1] an1, ar2 o gv dd ? memc1_mck[4:5]/ memc2_mcke[0:1] an25, ak1 o gv dd ? memc1_mck [0:1] al37, at36 o gv dd ? memc1_mck [2:3]/ memc2_mck [0:1] ap2, at2 o gv dd ? memc1_mck [4]/ memc2_mdm[8] an24 o gv dd ? memc1_mck [5]/ memc2_mdqs[8] al1 o gv dd ? mdic[0:1] ah6, ap30 i/o gv dd 10 secondary ddr sdram memory controller interface memc2_mecc[0:7] an16, ap18, am 16, am17, an17, ap13, ap15, an13 i/o gv dd ? memc2_mba[0:2] au12, au15, au13 o gv dd ? memc2_ma[0:14] at12, ap11, at13, at14, ar13, ar15, ar16, at16, at18, at17, ap10, ar20, ar17, ar14, ar11 ogv dd ? memc2_mwe au10 o gv dd ? memc2_mras at 1 1 o g v dd ? memc2_mcas au11 o gv dd ? pci pci_inta /irq_out/ ce_pf[5] a20 i/o lv dd 2 2 pci_reset_out /ce_pf[6] e19 i/o lv dd 2? pci_ad[31:30]/ce_pg[31:30] d20, d21 i/o lv dd 2? pci_ad[29:25]/ce_pg[29:25] a24, b23, c23, e23, a26 i/o ov dd ? pci_ad[24]/ce_ pg[24] b21 i/o lv dd 2? pci_ad[23:0]/ce_pg[23:0] c24, c25, d25, b25, e24, f24, a27, a28, f27, a30, c30, d30, e29, b31, c31, d31, d32, a32, c33, b33, f30, e31, a34, d33 i/o ov dd ? pci_c/be [3:0]/ce_pf[10:7] e22, b26, e28, f28 i/o ov dd ? pci_par/ce_pf[11] d28 i/o ov dd ? pci_frame /ce_pf[12] d26 i/o ov dd 5 pci_trdy /ce_pf[13] c27 i/o ov dd 5 pci_irdy /ce_pf[14] c28 i/o ov dd 5 pci_stop /ce_pf[15] b28 i/o ov dd 5 table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 67 pinout listings pci_devsel /ce_pf[16] e26 i/o ov dd 5 pci_idsel/ce_pf[17] f22 i/o ov dd ? pci_serr /ce_pf[18] b29 i/o ov dd 5 pci_perr /ce_pf[19] a29 i/o ov dd 5 pci_req [0]/ce_pf[20] f19 i/o lv dd 2? pci_req [1]/cpci_hs_es/ ce_pf[21] a21 i/o lv dd 2? pci_req [2]/ce_pf[22] c21 i/o lv dd 2? pci_gnt [0]/ce_pf[23] e20 i/o lv dd 2? pci_gnt [1]/cpci1_hs_led/ ce_pf[24] b20 i/o lv dd 2? pci_gnt [2]/cpci1_hs_enum / ce_pf[25] c20 i/o lv dd 2? pci_mode d36 i ov dd ? m66en/ce_pf[4] b37 i/o ov dd ? local bus controller interface lad[0:31] n32, n33, n35, n36, p37, p32, p34, r36, r35, r34, r33, t37, t35, t34, t33, u37, t32, u36, u34, v36, v35, w37, w35, v33, v32, w34, y36, w32, aa37, y33, aa35, aa34 i/o ov dd ? ldp[0]/ckstop_out ab37 i/o ov dd ? ldp[1]/ckstop_in ab36 i/o ov dd ? ldp[2]/lcs [6] ab35 i/o ov dd ? ldp[3]/lcs [7] aa33 i/o ov dd ? la[27:31] ac37, aa32, ac36, ac34, ad36 o ov dd ? lcs [0:5] ad33, ag37, af34, ae33, ad32, ah37 o ov dd ? lwe [0:3]/lsddqm[0:3]/lbs [0:3] ag35, ag34, ah36, ae32 o ov dd ? lbctl ad35 o ov dd ? lale m37 o ov dd ? lgpl0/lsda10/cfg_reset_source0 ab32 i/o ov dd ? lgpl1/lsdwe /cfg_reset_source1 ae37 i/o ov dd ? lgpl2/lsdras /loe ac33 o ov dd ? lgpl3/lsdcas/ cfg_reset_source2 ad34 i/o ov dd ? lgpl4/lgta /lupwait/lpbse ae35 i/o ov dd ? lgpl5/cfg_clkin_div af36 i/o ov dd ? lcke g36 o ov dd ? lclk[0] j33 o ov dd ? lclk[1]/lcs[6] j34 o ov dd ? table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 68 freescale semiconductor pinout listings lclk[2]/lcs[7] g37 o ov dd ? lsync_out f34 o ov dd ? lsync_in g35 i ov dd ? programmable interrupt controller mcp_out e34 o ov dd 2 irq 0 /mcp_in c37 i ov dd ? irq [1]/m1srcid[4]/m2srcid[4]/ lsrcid[4] f35 i/o ov dd ? irq [2]/m1dval/m2dval/ldval f36 i/o ov dd ? irq [3]/core_sreset h34 i/o ov dd ? irq [4:5] g33, g32 i/o ov dd ? irq [6]/lcs [6]/ckstop_out e35 i/o ov dd ? irq [7]/lcs [7]/ckstop_in h36 i/o ov dd ? duart uart1_sout/m1srcid[0]/ m2srcid[0]/lsrcid[0] e32 o ov dd ? uart1_sin/m1srcid[1]/ m2srcid[1]/lsrcid[1] b34 i/o ov dd ? uart1_cts /m1srcid[2]/ m2srcid[2]/lsrcid[2] c34 i/o ov dd ? uart1_rts /m1srcid[3]/ m2srcid[3]/lsrcid[3] a35 o ov dd ? i 2 c interface iic1_sda d34 i/o ov dd 2 iic1_scl b35 i/o ov dd 2 iic2_sda e33 i/o ov dd 2 iic2_scl c35 i/o ov dd 2 quicc engine block ce_pa[0] f8 i/o lv dd0 ? ce_pa[1:2] ah1, ag5 i/o ov dd ? ce_pa[3:7] f6, d4, c3, e5, a3 i/o lv dd 0? ce_pa[8] ag3 i/o ov dd ? ce_pa[9:12] f7, b3, e6, b4 i/o lv dd 0? ce_pa[13:14] ag1, af6 i/o ov dd ? ce_pa[15] b2 i/o lv dd 0? ce_pa[16] af4 i/o ov dd ? ce_pa[17:21] b16, a16, e17, a17, b17 i/o lv dd 1? table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 69 pinout listings ce_pa[22] af3 i/o ov dd ? ce_pa[23:26] c18, d18, e18, a18 i/o lv dd 1? ce_pa[27:28] af2, ae6 i/o ov dd ? ce_pa[29] b19 i/o lv dd 1? ce_pa[30] ae5 i/o ov dd ? ce_pa[31] f16 i/o lv dd 1? ce_pb[0:27] ae2, ae1, ad5, ad3, ad2, ac6, ac5, ac4, ac2, ac1, ab5, ab4, ab3, ab1 , aa6, aa4, aa2, y6, y4, y3, y2, y1, w6, w5 , w2, v5, v3, v2 i/o ov dd ? ce_pc[0:1] v1, u6 i/o ov dd ? ce_pc[2:3] c16, a15 i/o lv dd 1? ce_pc[4:6] u4, u3, t6 i/o ov dd ? ce_pc[7] c19 i/o lv dd 2? ce_pc[8:9] a4, c5 i/o lv dd 0? ce_pc[10:30] t5, t4, t2, t1, r5, r3, r1, c11, d12, f13, b10, c10, e12, a9, b8, d10, a 14, e15, b14, d15, ah2 i/o ov dd ? ce_pd[0:27] e11, d9, c8, f11, a7 , e9, c7, a6, f10, b6, d7, e8, b5, a5, c2, e4, f5, b1, d2 , g5, d1, e2, h6, f3, e1, f2, g3, h4 i/o ov dd ? ce_pe[0:31] k3, j2, f1, g2, j5, h3 , g1, h2, k6, j3, k5, k4, l6, p6, p4, p3, p1, n4, n5, n2, n1, m2, m3, m5, m6, l1, l2, l4, e14, c13, c14, b13 i/o ov dd ? ce_pf[0:3] f14, d13, a12, a11 i/o ov dd ? clocks pci_clk_out[0]/ce_pf[26] b22 i/o lv dd 2? pci_clk_out[1: 2]/ce_pf[27:28] d22, a23 i/o ov dd ? clkin e37 i ov dd ? pci_clock/pci_sync_in m36 i ov dd ? pci_sync_out/ce_pf[29] d37 i/o ov dd 3 jtag tck k33 i ov dd ? tdi k34 i ov dd 4 tdo h37 o ov dd 3 tms j36 i ov dd 4 trst l32 i ov dd 4 test test l35 i ov dd 7 test_sel au34 i gv dd 7 table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 70 freescale semiconductor pinout listings pmc quiesce b36 o ov dd ? system control poreset l37 i ov dd ? hreset l36 i/o ov dd 1 sreset m33 i/o ov dd 2 thermal management therm0 ap19 i gv dd ? therm1 at31 i gv dd ? power and ground signals av dd 1 k35 power for lbiu dll (1.2 v) av dd 1? av dd 2 k36 power for ce pll (1.2 v) av dd 2? av dd 5 am29 power for e300 pll (1.2 v) av dd 5? av dd 6 k37 power for system pll (1.2 v) av dd 6? gnd a2, a8, a13, a19, a22, a25, a31, a33, a36, b7, b12, b24, b27, b30, c4, c6, c9, c15, c26, c32, d3, d8, d11, d14, d17, d 19, d23, d27, e7, e13, e25, e30, e36, f4, f37, g 34, h1, h5, h32, h33, j4, j32, j37, k1, l3, l5, l33, l34, m1, m34, m35, n37, p2, p5, p35, p36, r4, t3, u1, u5, u35, v37, w1, w4, w33, w36, y34, aa3, aa5, ac3, ac32, ac35, ad1, ad37, ae4, ae34, ae 36, af33, ag4, ag6, ag32, ah35, aj1, aj4, aj32, aj35, aj37, ak36, al3, al34, am4, an6, an23, an30, ap8, ap12, ap14, ap16, ap17, ap20, ap25, ar6, ar8, ar9, ar19, ar24, ar31, ar35, ar37, at4, at10, at19, at20, at25, au14, au22, au28, au35 ??? gv dd ad4, ae3, af1, af5, af35, af37, ag2, ag36, ah33, ah34, ak5, am1, am 35, am37, an2, an10, an11, an12, an14, an32, an36, ap5, ap23, ap28, ar1, ar7, ar10, ar12, ar21, ar25, ar27, ar33, at15, at22, at28, at33, au2, au5, au16, au31, au36 power for ddr dram i/o voltage (2.5 or 1.8 v) gv dd ? table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 71 pinout listings lv dd 0 d5, d6 power for ucc1 ethernet interface (2.5 v, 3.3 v) lv dd 0? lv dd 1 c17, d16 power for ucc2 ethernet interface option 1 (2.5 v, 3.3 v) lv dd 1 9 lv dd 2 b18, e21 power for ucc2 ethernet interface option 2 (2.5 v, 3.3 v) lv dd 2 9 v dd c36, d29, d35, e16, f9, f12, f15, f17, f18, f20, f21, f23, f25, f26, f29, f31, f32, f33, g6, j6, k32, m32, n6, p33, r6, r32, u32, v6, y5, y32, ab6, ab33, ad6, af32, ak6, al6, am7, am9, am10, am11, am12, am13 , am14, am15, am18, am21, am25, am28, am32, an15, an21, an26, au9, au17 power for core (1.2 v) v dd ? ov dd a10, b9, b15, b32, c1, c 12, c22, c29, d24, e3, e10, e27, g4, h35, j1, j3 5, k2, m4, n3, n34, r2, r37, t36, u2, u33, v4, v34, w3, y35, y37, aa1, aa36, ab2, ab34 pci, 10/100 ethernet, and other standard (3.3 v) ov dd ? mvref1 an20 i ddr reference voltage ? mvref2 au32 i ddr reference voltage ? spare1 b11 i/o ov dd 8 spare3 ah32 ? gv dd 8 spare4 au18 ? gv dd 7 spare5 ap1 ? gv dd 8 table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 72 freescale semiconductor pinout listings this table shows the pin list of the mpc8358e tbga package. no connect nc am20, au19 ? ? ? notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd . 3. this output is actively driven during rese t rather than being thr ee-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. these are on die termination pins, used to control ddr2 memories internal termination resistance. 7. this pin must always be tied to gnd. 8. this pin must always be left not connected. 9. refer to mpc8360e powerquicc ii pro integrated co mmunications processor reference manual section on ?rgmii pins,? for information about the two ucc2 ethernet interface options. 10.it is recommended that mdic0 be tied to gnd using an 18.2 resistor and mdic1 be tied to ddr power using an 18.2 resistor for ddr2. table 67. mpc8358e tbga pinout listing signal package pin number pin type power supply notes ddr sdram memory controller interface memc1_mdq[0:63] aj34, ak33, al 33, al35, aj33, ak34, ak32, am36, an37, an35, ar34, at34, ap37, ap36, ar36, at35, ap34, ar32, ap32, am31, an33, am34, am33, am30, ap31, am27, ar30, at32, an29, ap29, an27, ar29, an8, an7, am8, am6, ap9, an9, at7, ap7, au6, ap6, ar4, ar3, at6, at5, ar5, at3, ap4, am5, ap3, an3, an5, al5, an4, am2, al2, ah5, ak3 , aj2, aj3, ah4, ak4, ah3 i/o gv dd ? memc_mecc[0:4]/msrcid[0:4] ap24, an22, am19, an19, am24 i/o gv dd ? memc_mecc[5]/mdval am23 i/o gv dd ? memc_mecc[6:7] am22, an18 i/o gv dd ? memc_mdm[0:8] al36, an34, ap33, an28,at9, au4, am3, aj6,ap27 ogv dd ? memc_mdqs[0:8] ak35, ap35, an31 , am26,at8, au3, al4, aj5, ap26 i/o gv dd ? memc_mba[0:1] au29, au30 o gv dd memc_mba[2] at30 o gv dd ? memc_ma[0:14] au21, ap22, ap21, at21, au25, au26, at23, ar26, au24, ar23, ar28, au23, ar22, au20, ar18 ogv dd ? memc_modt[0:3] ag33, aj36, at1, ak2 o gv dd 6 table 66. mpc8360e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 73 pinout listings memc_mwe at 2 6 o g v dd ? memc_mras at 2 9 o g v dd ? memc_mcas at 2 4 o g v dd ? memc_mcs [0:3] au27, at27, au8, au7 o gv dd ? memc_mcke[0:1] al32, au33 o gv dd 3 memc_mck[0:5] ak37, at37, an1, ar2, an25, ak1 o gv dd ? memc_mck [0:5] al37, at36, ap2, at2, an24, al1 o gv dd ? mdic[0:1] ah6, ap30 i/o gv dd 11 pci pci_inta /irq_out /ce_pf[5] a20 i/o lv dd 22 pci_reset_out /ce_pf[6] e19 i/o lv dd 2? pci_ad[31:30]/ce_pg[31:30] d20, d21 i/o lv dd 2? pci_ad[29:25]/ce_pg[29:25] a24, b23, c23, e23, a26 i/o ov dd ? pci_ad[24]/ce_ pg[24] b21 i/o lv dd 2? pci_ad[23:0]/ce_pg[23:0] c24, c25, d25, b25, e24, f24, a27, a28, f27, a30, c30, d30, e29, b31, c31, d31, d32, a32, c33, b33, f30, e31, a34, d33 i/o ov dd ? pci_c/be [3:0]/ce_pf[10:7] e22, b26, e28, f28 i/o ov dd ? pci_par/ce_pf[11] d28 i/o ov dd ? pci_frame /ce_pf[12] d26 i/o ov dd 5 pci_trdy /ce_pf[13] c27 i/o ov dd 5 pci_irdy /ce_pf[14] c28 i/o ov dd 5 pci_stop /ce_pf[15] b28 i/o ov dd 5 pci_devsel /ce_pf[16] e26 i/o ov dd 5 pci_idsel/ce_pf[17] f22 i/o ov dd ? pci_serr /ce_pf[18] b29 i/o ov dd 5 pci_perr /ce_pf[19] a29 i/o ov dd 5 pci_req [0]/ce_pf[20] f19 i/o lv dd 2? pci_req [1]/cpci_hs_es/ ce_pf[21] a21 i/o lv dd 2? pci_req [2]/ce_pf[22] c21 i/o lv dd 2? pci_gnt [0]/ce_pf[23] e20 i/o lv dd 2? pci_gnt [1]/cpci1_hs_led/ ce_pf[24] b20 i/o lv dd 2? pci_gnt [2]/cpci1_hs_enum / ce_pf[25] c20 i/o lv dd 2? table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 74 freescale semiconductor pinout listings pci_mode d36 i ov dd ? m66en/ce_pf[4] b37 i/o ov dd ? local bus controller interface lad[0:31] n32, n33, n35, n36, p37, p32, p34, r36, r35, r34, r33, t37, t35, t34, t33, u37, t32, u36, u34, v36, v35, w37, w35, v33, v32, w34, y36, w32, aa37, y33, aa35, aa34 i/o ov dd ? ldp[0]/ckstop_out ab37 i/o ov dd ? ldp[1]/ckstop_in ab36 i/o ov dd ? ldp[2]/lcs [6] ab35 i/o ov dd ? ldp[3]/lcs [7] aa33 i/o ov dd ? la[27:31] ac37, aa32, ac36, ac34, ad36 o ov dd ? lcs [0:5] ad33, ag37, af34, ae33, ad32, ah37 o ov dd ? lwe [0:3]/lsddqm[0:3]/lbs [0:3] ag35, ag34, ah36, ae32 o ov dd ? lbctl ad35 o ov dd ? lale m37 o ov dd ? lgpl0/lsda10/cfg_reset_source0 ab32 i/o ov dd ? lgpl1/lsdwe /cfg_reset_source1 ae37 i/o ov dd ? lgpl2/lsdras /loe ac33 o ov dd ? lgpl3/lsdcas /cfg_reset_source2 ad34 i/o ov dd ? lgpl4/lgta /lupwait/lpbse ae35 i/o ov dd ? lgpl5/cfg_clkin_div af36 i/o ov dd ? lcke g36 o ov dd ? lclk[0] j33 o ov dd ? lclk[1]/lcs[6] j34 o ov dd ? lclk[2]/lcs[7] g37 o ov dd ? lsync_out f34 o ov dd ? lsync_in g35 i ov dd ? programmable interrupt controller mcp_out e34 o ov dd 2 irq 0 /mcp_in c37 i ov dd ? irq [1]/m1srcid[4]/m2srcid[4]/ lsrcid[4] f35 i/o ov dd ? irq [2]/m1dval/m2dval/ldval f36 i/o ov dd ? irq [3]/core_sreset h34 i/o ov dd ? table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 75 pinout listings irq [4:5] g33, g32 i/o ov dd ? irq [6]/lcs [6]/ckstop_out e35 i/o ov dd ? irq [7]/lcs [7]/ckstop_in h36 i/o ov dd ? duart uart1_sout/m1srcid[0]/ m2srcid[0]/lsrcid[0] e32 o ov dd ? uart1_sin/m1srcid[1]/ m2srcid[1]/lsrcid[1] b34 i/o ov dd ? uart1_cts /m1srcid[2]/ m2srcid[2]/lsrcid[2] c34 i/o ov dd ? uart1_rts /m1srcid[3]/ m2srcid[3]/lsrcid[3] a35 o ov dd ? i 2 c interface iic1_sda d34 i/o ov dd 2 iic1_scl b35 i/o ov dd 2 iic2_sda e33 i/o ov dd 2 iic2_scl c35 i/o ov dd 2 quicc engine ce_pa[0] f8 i/o lv dd0 ? ce_pa[1:2] ah1, ag5 i/o ov dd ? ce_pa[3:7] f6, d4, c3, e5, a3 i/o lv dd 0? ce_pa[8] ag3 i/o ov dd ? ce_pa[9:12] f7, b3, e6, b4 i/o lv dd 0? ce_pa[13:14] ag1, af6 i/o ov dd ? ce_pa[15] b2 i/o lv dd 0? ce_pa[16] af4 i/o ov dd ? ce_pa[17:21] b16, a16, e17, a17, b17 i/o lv dd 1? ce_pa[22] af3 i/o ov dd ? ce_pa[23:26] c18, d18, e18, a18 i/o lv dd 1? ce_pa[27:28] af2, ae6 i/o ov dd ? ce_pa[29] b19 i/o lv dd 1? ce_pa[30] ae5 i/o ov dd ? ce_pa[31] f16 i/o lv dd 1? table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 76 freescale semiconductor pinout listings ce_pb[0:27] ae2, ae1, ad5, ad3, ad2, ac6, ac5, ac4, ac2, ac1, ab5, ab4, ab3, ab1 , aa6, aa4, aa2, y6, y4, y3, y2, y1, w6, w5 , w2, v5, v3, v2 i/o ov dd ? ce_pc[0:1] v1, u6 i/o ov dd ce_pc[2:3] c16, a15 i/o lv dd 1? ce_pc[4:6] u4, u3, t6 i/o ov dd ? ce_pc[7] c19 i/o lv dd 2? ce_pc[8:9] a4, c5 i/o lv dd 0? ce_pc[10:30] t5, t4, t2, t1, r5, r3, r1, c11, d12, f13, b10, c10, e12, a9, b8, d10, a 14, e15, b14, d15, ah2 i/o ov dd ? ce_pd[0:27] e11, d9, c8, f11, a7 , e9, c7, a6, f10, b6, d7, e8, b5, a5, c2, e4, f5, b1, d2 , g5, d1, e2, h6, f3, e1, f2, g3, h4 i/o ov dd ? ce_pe[0:31] k3, j2, f1, g2, j5, h3 , g1, h2, k6, j3, k5, k4, l6, p6, p4, p3, p1, n4, n5, n2, n1, m2, m3, m5, m6, l1, l2, l4, e14, c13, c14, b13 i/o ov dd ? ce_pf[0:3] f14, d13, a12, a11 i/o ov dd ? clocks pci_clk_out[0]/ce_pf[26] b22 i/o lv dd 2? pci_clk_out[1: 2]/ce_pf[27:28] d22, a23 i/o ov dd ? clkin e37 i ov dd ? pci_clock/pci_sync_in m36 i ov dd ? pci_sync_out/ce_pf[29] d37 i/o ov dd 3 jtag tck k33 i ov dd ? tdi k34 i ov dd 4 tdo h37 o ov dd 3 tms j36 i ov dd 4 trst l32 i ov dd 4 test test l35 i ov dd 7 test_sel au34 i gv dd 10 pmc quiesce b36 o ov dd ? system control table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 77 pinout listings poreset l37 i ov dd ? hreset l36 i/o ov dd 1 sreset m33 i/o ov dd 2 thermal management therm0 ap19 i gv dd ? therm1 at31 i gv dd ? power and ground signals av dd 1 k35 power for lbiu dll (1.2 v) av dd 1? av dd 2 k36 power for ce pll (1.2 v) av dd 2? av dd 5 am29 power for e300 pll (1.2 v) av dd 5? av dd 6 k37 power for system pll (1.2 v) av dd 6? gnd a2, a8, a13, a19, a22, a25, a31, a33, a36, b7, b12, b24, b27, b30, c4, c6, c9, c15, c26, c32, d3, d8, d11, d14, d17, d 19, d23, d27, e7, e13, e25, e30, e36, f4, f37, g 34, h1, h5, h32, h33, j4, j32, j37, k1, l3, l5, l33, l34, m1, m34, m35, n37, p2, p5, p35, p36, r4, t3, u1, u5, u35, v37, w1, w4, w33, w36, y34, aa3, aa5, ac3, ac32, ac35, ad1, ad37, ae4, ae34, ae 36, af33, ag4, ag6, ag32, ah35, aj1, aj4, aj32, aj35, aj37, ak36, al3, al34, am4, an6, an23, an30, ap8, ap12, ap14, ap16, ap17, ap20, ap25, ar6, ar8, ar9, ar19, ar24, ar31, ar35, ar37, at4, at10, at19, at20, at25, au14, au22, au28, au35 ??? gv dd ad4, ae3, af1, af5, af35, af37, ag2, ag36, ah33, ah34, ak5, am1, am 35, am37, an2, an10, an11, an12, an14, an32, an36, ap5, ap23, ap28, ar1, ar7, ar10, ar12, ar21, ar25, ar27, ar33, at15, at22, at28, at33, au2, au5, au16, au31, au36 power for ddr dram i/o voltage (2.5 or 1.8 v) gv dd ? lv dd 0 d5, d6 power for ucc1 ethernet interface (2.5 v, 3.3 v) lv dd 0? table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 78 freescale semiconductor pinout listings lv dd 1 c17, d16 power for ucc2 ethernet interface option 1 (2.5 v, 3.3 v) lv dd 1 9 lv dd 2 b18, e21 power for ucc2 ethernet interface option 2 (2.5 v, 3.3 v) lv dd 2 9 v dd c36, d29, d35, e16, f9, f12, f15, f17, f18, f20, f21, f23, f25, f26, f29, f31, f32, f33, g6, j6, k32, m32, n6, p33, r6, r32, u32, v6, y5, y32, ab6, ab33, ad6, af32, ak6, al6, am7, am9, am10, am11, am12, am13 , am14, am15, am18, am21, am25, am28, am32, an15, an21, an26, au9, au17 power for core (1.2 v) v dd ? ov dd a10, b9, b15, b32, c1, c 12, c22, c29, d24, e3, e10, e27, g4, h35, j1, j3 5, k2, m4, n3, n34, r2, r37, t36, u2, u33, v4, v34, w3, y35, y37, aa1, aa36, ab2, ab34 pci, 10/100 ethernet, and other standard (3.3 v) ov dd ? mvref1 an20 i ddr reference voltage ? mvref2 au32 i ddr reference voltage ? spare1 b11 i/o ov dd 8 spare3 ah32 ? gv dd 8 spare4 au18 ? gv dd 7 spare5 ap1 ? gv dd 8 table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 79 pinout listings no connect nc am16, am17, am20, an 13, an16, an17, ap10, ap11, ap13, ap15, ap18, ar11, ar13, ar14, ar15, ar16, ar17, ar20, at11, at12, at13, at14, at16, at17, at18, au10, au11, au12, au13, au15, au19 ??? notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd. 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd . 3. this output is actively driven during rese t rather than being thr ee-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. these are on die termination pins, used to control ddr2 memories internal termination resistance. 7. this pin must always be tied to gnd. 8. this pin must always be left not connected. 9. refer to mpc8360e powerquicc ii pro integrated co mmunications processor reference manual section on ?rgmii pins,? for information about the two ucc2 ethernet interface options. 10.this pin must always be tied to gv dd . 11.it is recommended that mdic0 be tied to gnd using an 18.2 resistor and mdic1 be tied to ddr power using an 18.2 resistor for ddr2. table 67. mpc8358e tbga pinout listing (continued) signal package pin number pin type power supply notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 80 freescale semiconductor pinout listings 21 clocking this figure shows the internal distribution of clocks within the mpc8360e. figure 54. mpc8360e clock subsystem core pll system ddrc2 lbiu lsync_in lsync_out lclk[0:2] memc2_mck[0:1] memc2_mck [0:1] core_clk e300 core csb_clk to rest clkin csb_clk mpc8360e ddrc2 memory local bus pci_clk_out[0:2] pci_sync_out pci_clk/ clock unit of the device lb_clk cfg_clkin_div pci clock pci_sync_in device memory device /n to local bus/ddrc2 controller dll /2 divider memc1_mck[0:5] memc1_mck [0:5] ddrc1 /2 ddr1_clk ddrc1 memory device pll quicc pll ce_clk to quicc engine block engine
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 81 pinout listings this figure shows the internal distribution of clocks within the mpc8358e. figure 55. mpc8358e clock subsystem the primary clock source for the device can be one of two input s, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. note that in pci host mode, the primary clock input also depends on whether pci clock outputs are selected with rcwh[pcickdrv]. when the device is configured as a pci host device (rcwh[pcihost] = 1) and pci clock output is selected (rcwh[pcickdrv] = 1), clkin is its primary input clock. clkin feeds the pci clock divider ( 2) and the multiplexors for pci_sync_out and pci_clk_out. the cfg_clkin_div configuration input selects whether clkin or clkin/2 is driven out on the pci_sync_out signal. the occr[pcioen n ] parameters enable the pci_clk_out n , respectively. pci_sync_out is connected externally to pci_sync_in to allow the internal clock subystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_ sync_in, with equal delay to all pci agent devices in the system, to allow the device to function. when the device is c onfigured as a pci agent device, pci_clk is the primary input core pll system lbiu lsync_in lsync_out lclk[0:2] core_clk e300 core csb_clk to rest clkin csb_clk mpc8358e local bus pci_clk_out[0:2] pci_sync_out pci_clk/ clock unit of the device lb_clk cfg_clkin_div pci clock pci_sync_in memory device /n dll divider memc1_mck[0:5] memc1_mck [0:5] ddrc /2 ddr1_clk ddrc memory device pll quicc pll ce_clk to quicc engine block engine
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 82 freescale semiconductor pinout listings clock. when the device is configured as a pci agent device the clkin and the cfg_clkin_div signals should be tied to gnd. when the device is configured as a pci host device (r cwh[pcihost] = 1) and pci clock output is disabled (rcwh[pcickdrv] = 0), clock distribution and balancing done externally on the board. ther efore, pci_sync_in is the primary input clock. as shown in figure 54 and figure 55 , the primary clock input (fr equency) is multiplied by the quicc engine block phase-locked loop (pll), the system pll, and the clock unit to create the quicc engine clock ( ce_clk ), the coherent system bus clock ( csb_clk ), the internal ddrc1 controller clock ( ddr1_clk ), and the internal clock for the local bus interface unit and ddr2 memory controller ( lb_clk ). the csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf in pci host mode, pci_sync_in (1 + cfg_clkin_div) is the clkin frequency; in pci agent mode, cfg_clkin_div must be pulled down (low), so pci_sync_in (1 + cfg_clkin_div) is the pci_clk frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fields in the reset configuration word low (rcwl) wh ich is loaded at power-on reset or by one of the hard-coded reset options. see chapter 4, ?reset, cl ocking, and initialization,? in the mpc8360e powerquicc ii pro integrated communications processor reference manual for more information on the clock subsystem. the ce_clk frequency is determined by the quicc engine pll mu ltiplication factor (rcwl[ce pmf) and the quicc engine pll division factor (rcwl[cepdf]) acco rding to the following equation: ce_clk = (primary clock input cepmf) (1 + cepdf) the internal ddr1_clk frequency is determined by the following equation: ddr1_clk = csb_clk (1 + rcwl[ddr1cm]) note that the lb_clk clock frequency (for ddrc2) is determined by rcwl[lbcm]. the internal ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the ddrc1 clock divider ( 2) to create the differential ddrc1 memory bus clock outputs (memc1_mck and memc1_mck ). however, the data rate is the same frequency as ddr1_clk . the internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk (1 + rcwl[lbcm]) note that lb_clk is not the external local bus or ddrc2 frequency; lb_clk passes through the a lb clock divider to create the external local bus clock outputs (lsync _out and lclk[0:2]). the lb clock divider ratio is controlled by lcrr[clkdiv]. additionally, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ratio that can be configured by a memory mapped register afte r the device comes out of reset. this table specifies which units have a configurable clock frequency. this table provides the oper ating frequencies for the tbga package un der recommended operating conditions (see table 2 ). all frequency combinations shown in the table below may not be available. maximum operating frequencies depend on the part table 68. configurable clock units unit default frequency options security core csb_clk /3 off, csb_clk 1 , csb_clk /2, csb_clk /3 1 with limitation, only for slow csb_clk rates, up to 166 mhz. pci and dma complex csb_clk off, csb_clk
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 83 system pll configuration ordered, see section 24.1, ?part numbers fully addressed by this document,? for part ordering details and contact your freescale sales representative or author ized distributor for more information. 21.1 system pll configuration the system pll is controlled by th e rcwl[spmf] and rcwl[svcod] parameters. this table shows the multiplication factor encodings fo r the system pll. table 69. operating frequencies for the tbga package characteristic 1 400 mhz 533 mhz 667 mhz 2 unit e300 core frequency ( core_clk ) 266?400 266?533 266?667 mhz coherent system bus frequency ( csb_clk ) 133?333 mhz quicc engine frequency 3 ( ce_clk ) 266?500 mhz ddr and ddr2 memory bus frequency (mclk) 4 100?166.67 mhz local bus frequency (lclk n ) 5 16.67?133 mhz pci input frequency (clkin or pci_clk) 25?66.67 mhz security core maximum internal operating frequency 133 133 166 mhz notes: 1. the clkin frequency, rcwl[spmf], an d rcwl[corepll] settings must be chosen such that the resulting csb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2. the 667 mhz core frequency is based on a 1.3 v v dd supply voltage. 3. the 500 mhz qe frequency is based on a 1.3 v v dd supply voltage. 4. the ddr data rate is 2x the ddr memory bus frequency. 5. the local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on lcrr[clkdiv]) which is in turn 1 or 2 the csb_clk frequency (depending on rcwl[lbcm]). table 70. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 16 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 84 freescale semiconductor system pll configuration the rcwl[svcod] denotes the system pll vco in ternal frequency as shown in this table. note the vco divider must be set properly so that the system vco frequency is in the range of 600?1400 mhz. the system vco frequency is derived from the following equations: ? csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf ? system vco frequency = csb_clk vco divider (if both rcwl[ddrcm] and rcwl[lbcm] are cleared) or ? system vco frequency = 2 csb_clk vco divider (if either rcwl[ ddrcm] or rcwl[lbcm] are set). as described in section 21, ?clocking,? the lbcm, ddrcm, and spmf parameters in the reset configuration word low and the cfg_clkin_div configuration input signal select the rati o between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). this table shows the expected fre quency values for the csb frequency for select csb_clk to clkin/pci_sync_in ratios. 1100 12 1101 13 1110 14 1111 15 table 71. system pll vco divider rcwl[svcod] vco divider 00 4 01 8 10 2 11 reserved table 72. csb frequency options cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2:1 133 low 0011 3:1 100 200 low 0100 4:1 100 133 266 low 0101 5:1 125 166 333 table 70. system pll multiplication factors (continued) rcwl[spmf] system pll multiplication factor
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 85 system pll configuration low 0110 6:1 100 150 200 low 0111 7:1 116 175 233 low 1000 8:1 133 200 266 low 1001 9:1 150 225 300 low 1010 10:1 166 250 333 low 1011 11:1 183 275 low 1100 12:1 200 300 low 1101 13:1 216 325 low 1110 14:1 233 low 1111 15:1 250 low 0000 16:1 266 high 0010 2:1 133 high 0011 3:1 100 200 high 0100 4:1 133 266 high 0101 5:1 166 333 high 0110 6:1 200 high 0111 7:1 233 high 1000 8:1 high 1001 9:1 high 1010 10:1 high 1011 11:1 high 1100 12:1 high 1101 13:1 high 1110 14:1 high 1111 15:1 high 0000 16:1 1 cfg_clkin_div is only used for host mode; clkin must be tied low and cfg_clkin_div must be pulled down (low) in agent mode. 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. table 72. csb frequency options (continued) cfg_clkin_div at reset 1 spmf csb_clk : input clock ratio 2 input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 86 freescale semiconductor core pll configuration 21.2 core pll configuration rcwl[corepll] selects the ratio between th e internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). this table shows the encodings for rcwl[corepll]. corepll values not listed in this table should be considered reserved. note core vco frequency = core frequency vco divider. the vco divider (rcwl[corepll[0:1]]) must be set properly so that the core vco frequency is in the range of 800?1800 mhz. having a core frequency below the csb frequency is not a possible option because the core frequency mu st be equal to or greater than the csb frequency. table 73. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 0?1 2?5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 11.5:1 2 01 0001 11.5:1 4 10 0001 11.5:1 8 11 0001 11.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 12.5:1 2 01 0010 12.5:1 4 10 0010 12.5:1 8 11 0010 12.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 87 quicc engine block pll configuration 21.3 quicc engine block pll configuration the quicc engine block pll is controlled by the rcwl[c epmf], rcwl[cepdf], and rcwl[cevcod] parameters. this table shows the multiplication factor encodings for the quicc engine block pll. table 74. quicc engine block pll multiplication factors rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf]) 00000 0 16 00001 0 reserved 00010 0 2 00011 0 3 00100 0 4 00101 0 5 00110 0 6 00111 0 7 01000 0 8 01001 0 9 01010 0 10 01011 0 11 01100 0 12 01101 0 13 01110 0 14 01111 0 15 10000 0 16 10001 0 17 10010 0 18 10011 0 19 10100 0 20 10101 0 21 10110 0 22 10111 0 23 11000 0 24 11001 0 25 11010 0 26 11011 0 27 11100 0 28
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 88 freescale semiconductor quicc engine block pll configuration the rcwl[cevcod] denotes the quicc engine block pll vco internal frequency as shown in this table. note the vco divider (rcwl[cevcod]) must be set properly so that the quicc engine block vco frequency is in the range of 600?1400 mhz. the quicc engine block frequency is not restricted by the csb and core frequencies. the csb, core, and quicc engine block frequencies should be selected according to the perf ormance requirements. 11101 0 29 11110 0 30 11111 0 31 00011 1 1.5 00101 1 2.5 00111 1 3.5 01001 1 4.5 01011 1 5.5 01101 1 6.5 01111 1 7.5 10001 1 8.5 10011 1 9.5 10101 1 10.5 10111 1 11.5 11001 1 12.5 11011 1 13.5 11101 1 14.5 note: 1. reserved modes are not listed. table 75. quicc engine block pll vco divider rcwl[cevcod] vco divider 00 4 01 8 10 2 11 reserved table 74. quicc engine block pll multiplication factors (continued) rcwl[cepmf] rcwl[cepdf] quicc engine pll multiplication factor = rcwl[cepmf]/ (1 + rcwl[cepdf])
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 89 suggested pll configurations the quicc engine block vco frequency is derived from the following equations: ce_clk = (primary clock input cepmf) (1 + cepdf) qe vco frequency = ce_clk vco divider (1 + cepdf) 21.4 suggested pll configurations to simplify the pll configurations, the device might be separated into two clock domains. the first domain contains the csb pll and the core pll. the core pll is connected serially to the csb pll, and has the csb_clk as its input clock. the second clock domain has the quicc engine block pll. the clock do mains are independent, and each of their plls are configured separately. both of the domains has one common input clock. this table shows suggested pll configurations for 33 and 66 mhz input clocks and illustrates each of the clock domains separately. any combinat ion of clock domains setting with same input clock are valid. refer to section 21, ?clocking,? for the appropriate operating frequencies for your device. table 76. suggested pll configurations conf no. 1 spmf core pll cepmf cepdf input clock freq (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 533 (mhz) 667 (mhz) 33 mhz clkin/pci_sync_in options s1 0100 0000100 ? ? 33 133 266 ? ? s2 0100 0000101 ? ? 33 133 333 ? ? s3 0101 0000100 ? ? 33 166 333 ? ? s4 0101 0000101 ? ? 33 166 416 ? ? ? s5 0110 0000100 ? ? 33 200 400 ? ? s6 0110 0000110 ? ? 33 200 600 ? ? ? s7 0111 0000011 ? ? 33 233 350 ? ? s8 0111 0000100 ? ? 33 233 466 ? ? ? s9 0111 0000101 ? ? 33 233 583 ? ? ? s10 1000 0000011 ? ? 33 266 400 ? ? s11 1000 0000100 ? ? 33 266 533 ? ? ? s12 1000 0000101 ? ? 33 266 667 ? ? ? s13 1001 0000010 ? ? 33 300 300 ? ? s14 1001 0000011 ? ? 33 300 450 ? ? ? s15 1001 0000100 ? ? 33 300 600 ? ? ? s16 1010 0000010 ? ? 33 333 333 ? ? s17 1010 0000011 ? ? 33 333 500 ? ? ? s18 1010 0000100 ? ? 33 333 667 ? ? ? c1 ? ? 01001 0 33 ? ? 300 ? c2 ? ? 01100 0 33 ? ? 400 ? c3 ? ? 01110 0 33 ? ? 466 ? ? c4 ? ? 01111 0 33 ? ? 500 ? ?
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 90 freescale semiconductor suggested pll configurations the following steps describe how to use above table. see example 1 . 2. choose the up or down sections in the tabl e according to input clock rate 33 mhz or 66 mhz. 3. select a suitable csb and core clock rates from table 76 . copy the spmf and core pll configuration bits. 4. select a suitable quicc engine block clock rate from table 76 . copy the cepmf and cepdf configuration bits. 5. insert the chosen spmf, corepll, cepmf and cepdf to the rcwl fields, respectively. c5 ? ? 10000 0 33 ? ? 533 ? ? c6 ? ? 10001 0 33 ? ? 566 ? ? 66 mhz clkin/pci_sync_in options s1h 0011 0000110 ? ? 66 200 400 ? ? s2h 0011 0000101 ? ? 66 200 500 ? ? ? s3h 0011 0000110 ? ? 66 200 600 ? ? ? s4h 0100 0000011 ? ? 66 266 400 ? ? s5h 0100 0000100 ? ? 66 266 533 ? ? ? s6h 0100 0000101 ? ? 66 266 667 ? ? ? s7h 0101 0000010 ? ? 66 333 333 ? ? s8h 0101 0000011 ? ? 66 333 500 ? ? ? s9h 0101 0000100 ? ? 66 333 667 ? ? ? c1h ? ? 00101 0 66 ? ? 333 ? c2h ? ? 00110 0 66 ? ? 400 ? c3h ? ? 00111 0 66 ? ? 466 ? ? c4h ? ? 01000 0 66 ? ? 533 ? ? c5h ? ? 01001 0 66 ? ? 600 ? ? note: 1. the conf no. consist of prefix, an index and a postfix. the prefix ?s? and ?c? stands for ?syset? and ?ce? respectively. the postfix ?h? stands for ?high input clock.??the index is a serial number. table 76. suggested pll configurations (continued) conf no. 1 spmf core pll cepmf cepdf input clock freq (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 533 (mhz) 667 (mhz)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 91 thermal characteristics example 1. sample table use ? example a. to configure the device with csb clock rate of 266 mhz, core rate of 400 mhz, and quicc engine clock rate 300 mhz while the input clock rate is 33 mhz. conf no. ?s10? and ?c1? are selected from table 76 . spmf is 1000, corpll is 0000011, cepmf is 01001, and cepdf is 0. ? example b. to configure the device with csbcsb clock rate of 266 mhz, core rate of 533 mhz and quicc engine clock rate 400 mhz while the input clock rate is 66 mhz. conf no. ?s5h? and ?c2h? are selected from table 76 . spmf is 0100, corpll is 0000100, cepmf is 00110, and cepdf is 0. 22 thermal this section describes the thermal specifications of the mpc8360e/58e. 22.1 thermal characteristics this table provides the package thermal characteristics for the 37. 5 mm 37.5 mm 740-tbga package. index spmf core pll cepmf cepdf input clock (mhz) csb freq (mhz) core freq (mhz) quicc engine freq (mhz) 400 (mhz) 533 (mhz) 667 (mhz) a 1000 0000011 01001 0 33 266 400 300 ? b 0100 0000100 00110 0 66 266 533 400 ? table 77. package thermal characteristics for the tbga package characteristic symbol value unit notes junction-to-ambient natural convection on single-layer board (1s) r ja 15 c/w 1 , 2 junction-to-ambient natural convection on four-layer board (2s2p) r ja 11 c/w 1 , 3 junction-to-ambient (@1 m/s) on single-layer board (1s) r jma 10 c/w 1 , 3 junction-to-ambient (@ 1 m/s) on four-layer board (2s2p) r jma 8 c/w 1 , 3 junction-to-ambient (@ 2 m/s) on single-layer board (1s) r jma 9 c/w 1 , 3 junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) r jma 7 c/w 1 , 3 junction-to-board thermal r jb 4.5 c/w 4 junction-to-case thermal r jc 1.1 c/w 5
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 92 freescale semiconductor thermal management information 22.2 thermal management information for the following sections, p d = (v dd i dd ) + p i/o where p i/o is the power dissipation of the i/o drivers. see table 6 for typical power dissipations values. 22.2.1 estimation of junction temperature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperatur e for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an industry standa rd value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single-layer board is appropriate for a tightly packed printed-circuit board. the value obtained on the board with the in ternal planes is usually approp riate if the board has low pow er dissipation and the components are well separate d. test cases have demonstrated that er rors of a factor of two (in the quantity t j ? t a ) are possible. 22.2.2 estimation of junction temperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequately pred icted from the junction-to-ambient thermal resistance. the thermal performance of any component is strongly dependent on the power dissipation of surrounding components. additionally, the ambient temperature varies widely within the application. for many natural co nvection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. speci fying the local ambient conditions explicitly as the board temperature provides a more precis e description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: junction-to-package natural convection on top jt 1 c/w 6 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissi pation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 and semi g38-87 with the single layer board horizontal. 3. per jedec jesd51-6 with the board hori zontal. 1 m/sec is approximately equal to 200 linear feet per minute (lfm). 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not avai lable, the thermal characterization parameter is written as psi-jt. table 77. package thermal characteristics for the tbga package (continued) characteristic symbol value unit notes
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 93 thermal management information t j = t b + ( r jb p d ) where: t j = junction temperature ( c) t b = board temperature at the package perimeter ( c) r ja = junction to board thermal resistance ( c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air can be i gnored, acceptable predictions of j unction temperature can be made. the application board should be similar to the thermal test conditi on: the component is soldered to a board with internal plane s. 22.2.3 experimental determinat ion of junction temperature to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: t j = junction temperature ( c) t t = thermocouple temperat ure on top of package ( c) jt = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoi d measurement errors caused by cooling effects of the thermocouple wire. 22.2.4 heat sinks and junction -to-ambient thermal resistance in some application environments , a heat sink is required to pr ovide the necessary thermal management of the device. when a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambien t thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device related and cannot be influenced by the user. the user controls the therma l environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the airflow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal pe rformance has been simulated with a few commercially available heat sink s. the heat sink choice is determined by the application environment (temperature, airflow, adjacent component power dissip ation) and the physical space available. b ecause there is not a standard application environment, a standard heat sink is not required.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 94 freescale semiconductor thermal management information this table shows heat sinks and junction-to- ambient thermal resistance for tbga package. accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resist ance table. more detailed thermal mode ls can be made available on request. heat sink vendors include the following: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com table 78. heat sinks and junction-to-ambient thermal resistance of tbga package heat sink assuming thermal grease airflow 35 35 mm tbga junction-to-ambient thermal resistance aavid 30 30 9.4 mm pin fin natural convention 10.7 aavid 30 30 9.4 mm pin fin 1 m/s 6.2 aavid 30 30 9.4 mm pin fin 2 m/s 5.3 aavid 31 35 23 mm pin fin natural convention 8.1 aavid 31 35 23 mm pin fin 1 m/s 4.4 aavid 31 35 23 mm pin fin 2 m/s 3.7 wakefield, 53 53 25 mm pin fin natural convention 5.4 wakefield, 53 53 25 mm pin fin 1 m/s 3.2 wakefield, 53 53 25 mm pin fin 2 m/s 2.4 mei, 75 85 12 no adjacent board, extrusion natural convention 6.4 mei, 75 85 12 no adjacent board, extrusion 1 m/s 3.8 mei, 75 85 12 no adjacent board, extrusion 2 m/s 2.5 mei, 75 85 12 mm, adjacent board, 40 mm side bypass 1 m/s 2.8
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 95 heat sink attachment millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-millennium.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendor s include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 22.3 heat sink attachment when attaching heat sinks to these devices, an interface material is required. the best method is to use thermal grease and a spring clip. the spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. avoid attachment forces which would lift the edge of the package or peel the package from the board. such peeling forces reduce the solder joint lifetime of the package. recommen ded maximum force on the top of the package is 10 lb force (4.5 kg force). if an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance veri fied under the application requirements.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 96 freescale semiconductor system clocking 22.3.1 experimental determination of the junction temperature with a heat sink when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally require d in the heat sink. minimizing the size of the clearance is important to minimize the ch ange in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. t j = t c + ( r jc p d ) where: t j = junction temperature ( c) t c = case temperature of the package ( c) r jc = junction to case thermal resistance ( c/w) p d = power dissipation (w) 23 system design information this section provides electrical and th ermal design recommendations for succe ssful application of the mpc8360e/58e. additional information can be found in mpc8360e/mpc8358e powerquicc design checklist (an3097). 23.1 system clocking the device includes two plls, as follows. ? the platform pll (av dd 1) generates the platform clock from the ex ternally supplied clkin input. the frequency ratio between the platform and clkin is selected using the platform pll ratio configuration bits as described in section 21.1, ?system pll configuration.? ? the e300 core pll (av dd 2) generates the core clock as a slave to th e platform clock. the frequency ratio between the e300 core clock and the platform cl ock is selected using the e300 pll ratio configuration bits as described in section 21.2, ?core pll configuration.? 23.2 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd 1, av dd 2, respectively). the av dd level should always be equivalent to v dd , and preferably these voltages are derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the p lls, but the recommended solution is to provide five independent filter circuits as illustrated in figure 56 , one to each of the five av dd pins. by providing independe nt filters to each pll, the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the plls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitors with minimum effective series inductance (esl). cons istent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), mu ltiple small capacitors of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from th e capacitors to the av dd pin, which is on the periphery of package, without the inductance of vias.
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 97 decoupling recommendations this figure shows the pll power supply filter circuit. figure 56. pll power supply filter circuit 23.3 decoupling recommendations due to large address and data buses as we ll as high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driv ing large capacitive loads. this noise must be prevented from reaching other components in th e device system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , gv dd , and lv dd pins of the device. these decoupling capacitors should receive their power from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, utilizing s hort traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount tech nology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. additionally, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rati ng to ensure the quick response time nece ssary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 23.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the device. 23.5 output buffer dc impedance the device drivers are characterized over process, voltage, and temperature. for a ll buses, the driver is a push-pull single-en ded driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is vari ed until the pad voltage is ov dd /2 (see figure 57 ). the output impedance is the average of two components, the resistances of th e pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistan ce of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. v dd av dd n 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 98 freescale semiconductor configuration pin muxing figure 57. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be f ound by making two measurements. first, th e output voltage is measured while driving logic 1 without an exte rnal differential termination re sistor. the measured voltage is v 1 = r source i source . second, the output voltage is meas ured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 = 1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . this table summarizes the signal im pedance targets. the driver impe dance are targeted at minimum v dd , nominal ov dd , 105 c. 23.6 configuration pin muxing the device provides the user with power-on configuration optio ns that can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see cust omer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as i nputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the i nput receiver is disabled and th e i/o circuit takes on its normal function. careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of t he pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. table 79. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci ddr dram symbol unit r n 42 target 25 target 20 target z 0 w r p 42 target 25 target 20 target z 0 w differential na na na z diff w note: nominal supply voltages. see ta bl e 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 99 pull-up resistor requirements 23.7 pull-up resistor requirements the device requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including i 2 c pins, ethernet management mdio pin, and epic interrupt pins. for more information on required pull-up resistors and the connections required for the jtag interface, see mpc8360e/mpc8358e powerq uicc design checklist (an3097). 24 ordering information 24.1 part numbers fully addressed by this document this table provides the freescale part numbering nomenclature for the mpc8360e/58e. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your lo cal freescale sales office. additionally to the processor frequency, the part numbering scheme also includes an application modifier, which may specify special application conditions. each part num ber also contains a revision code that refers to the die mask revision number. this table shows the svr settings by device and package type. table 80. part numbering nomenclature 1 mpc nnnn e t pp aa a a a product code part identifier encryption acceleration temperature range package 2 processor frequency 3 platform frequency quicc engine frequency die revision mpc 8358 blank = not included e = included blank = 0 c t a to 105 c t j c= ?40 c t a to 105 c t j zu = tbga vv = tbga (no lead) e300 core speed ad = 266 mhz ag = 400 mhz d = 266 mhz e = 300 mhz g = 400 mhz a = rev. 2.1 silicon 8360 e300 core speed ag = 400 mhz aj = 533 mhz al = 667 mhz d = 266 mhz f = 333 mhz g = 400 mhz h = 500 mhz a = rev. 2.1 silicon mpc (rev. 2.0 silicon only) 8360 blank = not included e = included 0 c t a to 70 c t j zu = tbga vv = tbga (no lead) e300 core speed ah = 500 mhz al = 667 mhz f = 333 mhz g = 400 mhz h = 500 mhz ? notes: 1. not all processor, platform, and quicc engine block frequency combinations are supported. for available frequency combinations, contact your local freescale sales office or authorized distributor. 2. see section 20, ?package and pin listings,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, part s addressed by part number specifications may support other maximum core frequencies. table 81. svr settings device package svr (rev. 2.0) svr (rev. 2.1) mpc8360e tbga 0x8048_0020 0x8048_0021 mpc8360 tbga 0x8049_0020 0x8049_0021
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 100 freescale semiconductor part numbers fully addressed by this document 25 document revision history this table provides a revision history for this document. mpc8358e tbga 0x804a_0020 0x804a_0021 mpc8358 tbga 0x804b_0020 0x804b_0021 table 82. revision history rev. number date substantive change(s) 5 09/2011 ? section 2.2.1, ?power-up sequencing ?, added the current limitation ?3a to 5a? for the excessive current. ? section 2.1.2, ?power supply voltage specification , updated the characteristic for tbga (mpc8358 & mpc8360 device) with specific frequency for core and pll voltages. ? added table footnote 3 to ta b l e 2 . ? applied table footnotes 1 and 2 to ta bl e 1 0 . ? removed table footnotes from ta bl e 1 9 . ? applied table footnote 8 to the last row of ta b l e 4 0 . ? applied table footnotes 8 and 9 to ta bl e 4 1 . ? applied table footnotes 2and 3 to ta b l e 4 5 . ? removed table footnotes from ta bl e 4 6 . ? applied table footnote to last three rows of ta bl e 6 5 . 4 01/2011 ? updated references to the lcrr register throughout ? removed references to ddr dll mode in section 6.2.2, ?ddr and ddr2 sdram output ac timing specifications .? ? changed ?junction-to-case? to ?junction-to-ambient? in section 22.2.4, ?heat sinks and junction-to-ambient thermal resistance ,? and ta bl e 7 8 , ?heat sinks and junction-to-ambient thermal resistance of tbga package,? titles. table 81. svr settings (continued) device package svr (rev. 2.0) svr (rev. 2.1)
mpc8360e/mpc8358e powerquicc ii pro processor revision 2.x tbga silicon hardware specifications, rev. 5 freescale semiconductor 101 part numbers fully addressed by this document 3 03/2010 ? changed references to rcwh[pcicken] to rcwh[pcickdrv]. ?in ta b l e 2 , added extended temperature characteristics. ? added figure 6 , ?ddr input timing diagram.? ? in figure 53 , ?mechanical dimensions and bottom surface nomenclature of the tbga package,? removed watermark. ? updated the title of ta bl e 1 9 ,?ddr sdram input ac timing specifications.? ?in ta b l e 2 0 , ?ddr and ddr2 sdram input ac timing specif ications mode,? changed table subtitle. ?in ta b l e 2 7 ? ta bl e 3 0 , and ta b l e 3 3 ? ta bl e 3 4 , changed the rise and fall time specifications to reference 20?80% and 80?20% of the voltage supply, respectively. ?in ta b l e 3 8 , ?ieee 1588 timer ac specifications,? changed first parameter to ?timer clock frequency.? ?in ta b l e 4 5 , ?i2c ac electrical specificatio ns,? changed units to ?ns? for t i2dvkh . ?in ta b l e 6 6 , ?mpc8360e tbga pinout listing,? and ta bl e 6 7 ?mpc8358e tbga pinout listing , added note 7: ?this pin must always be tied to gnd? to t he test pin and added a note to spare1 stating: ?this pin must always be left not connected.? ?in section 4, ?clock input timing ,? added note regarding rise/fall time on quicc engine block input pins. ? added section 4.3, ?gigabit reference clock input timing .? ? updated section 8.1.1, ?10/100/1000 etherne t dc electrical characteristics .? ?in section 20.3, ?pinout listings ,? added sentence stating ?refer to an3097, ?mpc8360/mpc8358e powerquicc design checklist,? for proper pin termination and usage.? ?in section 21, ?clocking ,? removed statement: ?the occr[pci cdn] parameters select whether clkin or clkin/2 is driven out on the pci_clk_outn signals.? ?in section 21.1, ?system pll configuration ,? updated the system vco frequency conditions. ?in ta b l e 8 0 , added extended temperature characteristics. 2 12/2007 initial release. table 82. revision history (continued) rev. number date substantive change(s)
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